1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #include <common.h> 7 8 #include <asm/io.h> 9 #include <asm/types.h> 10 11 #include <mach/tlb.h> 12 #include <mach/ddr.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 static inline int vcoreiii_train_bytelane(void) 17 { 18 int ret; 19 20 ret = hal_vcoreiii_train_bytelane(0); 21 22 if (ret) 23 return ret; 24 ret = hal_vcoreiii_train_bytelane(1); 25 26 return ret; 27 } 28 29 int vcoreiii_ddr_init(void) 30 { 31 int res; 32 33 if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) 34 & ICPU_MEMCTRL_STAT_INIT_DONE)) { 35 hal_vcoreiii_init_memctl(); 36 hal_vcoreiii_wait_memctl(); 37 if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane()) 38 hal_vcoreiii_ddr_failed(); 39 } 40 #if (CONFIG_SYS_TEXT_BASE != 0x20000000) 41 res = dram_check(); 42 if (res == 0) 43 hal_vcoreiii_ddr_verified(); 44 else 45 hal_vcoreiii_ddr_failed(); 46 47 /* Clear boot-mode and read-back to activate/verify */ 48 clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 49 ICPU_GENERAL_CTRL_BOOT_MODE_ENA); 50 readl(BASE_CFG + ICPU_GENERAL_CTRL); 51 #else 52 res = 0; 53 #endif 54 return res; 55 } 56 57 int print_cpuinfo(void) 58 { 59 printf("MSCC VCore-III MIPS 24Kec\n"); 60 61 return 0; 62 } 63 64 int dram_init(void) 65 { 66 while (vcoreiii_ddr_init()) 67 ; 68 69 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 70 return 0; 71 } 72