1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #include <common.h> 7 8 #include <asm/io.h> 9 #include <asm/types.h> 10 11 #include <mach/tlb.h> 12 #include <mach/ddr.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M 17 #define MSCC_RAM_TLB_SIZE SZ_64M 18 #define MSCC_ATTRIB2 MMU_REGIO_INVAL 19 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M 20 #define MSCC_RAM_TLB_SIZE SZ_64M 21 #define MSCC_ATTRIB2 MMU_REGIO_RW 22 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M 23 #define MSCC_RAM_TLB_SIZE SZ_256M 24 #define MSCC_ATTRIB2 MMU_REGIO_INVAL 25 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M 26 #define MSCC_RAM_TLB_SIZE SZ_256M 27 #define MSCC_ATTRIB2 MMU_REGIO_RW 28 #else 29 #define MSCC_RAM_TLB_SIZE SZ_512M 30 #define MSCC_ATTRIB2 MMU_REGIO_RW 31 #endif 32 33 /* NOTE: lowlevel_init() function does not have access to the 34 * stack. Thus, all called functions must be inlined, and (any) local 35 * variables must be kept in registers. 36 */ 37 void vcoreiii_tlb_init(void) 38 { 39 register int tlbix = 0; 40 41 /* 42 * Unlike most of the MIPS based SoCs, the IO register address 43 * are not in KSEG0. The mainline linux kernel built in legacy 44 * mode needs to access some of the registers very early in 45 * the boot and make the assumption that the bootloader has 46 * already configured them, so we have to match this 47 * expectation. 48 */ 49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, 50 MMU_REGIO_RW); 51 52 #if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO 53 /* 54 * If U-Boot is located in NOR then we want to be able to use 55 * the data cache in order to boot in a decent duration 56 */ 57 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, 58 MMU_REGIO_RO_C); 59 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, 60 MMU_REGIO_RO_C); 61 62 /* 63 * Using cache for RAM also helps to improve boot time. Thanks 64 * to this the time to relocate U-Boot in RAM went from 2.092 65 * secs to 0.104 secs. 66 */ 67 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, 68 MSCC_ATTRIB2); 69 70 /* Enable caches by clearing the bit ERL, which is set on reset */ 71 write_c0_status(read_c0_status() & ~BIT(2)); 72 #endif /* CONFIG_SYS_TEXT_BASE */ 73 } 74 75 int mach_cpu_init(void) 76 { 77 /* Speed up NOR flash access */ 78 writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 79 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); 80 /* 81 * Legacy and mainline linux kernel expect that the 82 * interruption map was set as it was done by redboot. 83 */ 84 writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); 85 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); 86 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); 87 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); 88 89 return 0; 90 } 91