1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #include <common.h> 7 8 #include <asm/io.h> 9 #include <asm/types.h> 10 11 #include <mach/tlb.h> 12 #include <mach/ddr.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M 17 #define MSCC_RAM_TLB_SIZE SZ_64M 18 #define MSCC_ATTRIB2 MMU_REGIO_INVAL 19 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M 20 #define MSCC_RAM_TLB_SIZE SZ_64M 21 #define MSCC_ATTRIB2 MMU_REGIO_RW 22 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M 23 #define MSCC_RAM_TLB_SIZE SZ_256M 24 #define MSCC_ATTRIB2 MMU_REGIO_INVAL 25 #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M 26 #define MSCC_RAM_TLB_SIZE SZ_256M 27 #define MSCC_ATTRIB2 MMU_REGIO_RW 28 #else 29 #define MSCC_RAM_TLB_SIZE SZ_512M 30 #define MSCC_ATTRIB2 MMU_REGIO_RW 31 #endif 32 33 /* NOTE: lowlevel_init() function does not have access to the 34 * stack. Thus, all called functions must be inlined, and (any) local 35 * variables must be kept in registers. 36 */ 37 void vcoreiii_tlb_init(void) 38 { 39 register int tlbix = 0; 40 41 /* 42 * Unlike most of the MIPS based SoCs, the IO register address 43 * are not in KSEG0. The mainline linux kernel built in legacy 44 * mode needs to access some of the registers very early in 45 * the boot and make the assumption that the bootloader has 46 * already configured them, so we have to match this 47 * expectation. 48 */ 49 create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, 50 MMU_REGIO_RW); 51 #ifdef CONFIG_SOC_LUTON 52 create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, 53 MMU_REGIO_RW); 54 #endif 55 56 #if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO 57 /* 58 * If U-Boot is located in NOR then we want to be able to use 59 * the data cache in order to boot in a decent duration 60 */ 61 create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, 62 MMU_REGIO_RO_C); 63 create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, 64 MMU_REGIO_RO_C); 65 66 /* 67 * Using cache for RAM also helps to improve boot time. Thanks 68 * to this the time to relocate U-Boot in RAM went from 2.092 69 * secs to 0.104 secs. 70 */ 71 create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, 72 MSCC_ATTRIB2); 73 74 /* Enable caches by clearing the bit ERL, which is set on reset */ 75 write_c0_status(read_c0_status() & ~BIT(2)); 76 #endif /* CONFIG_SYS_TEXT_BASE */ 77 } 78 79 int mach_cpu_init(void) 80 { 81 /* Speed up NOR flash access */ 82 #ifdef CONFIG_SOC_LUTON 83 writel(ICPU_PI_MST_CFG_TRISTATE_CTRL + 84 ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG); 85 86 writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + 87 ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 88 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); 89 #else 90 #if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL) 91 writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 92 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); 93 #endif 94 #if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT) 95 writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + 96 ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 97 ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG); 98 #endif 99 /* 100 * Legacy and mainline linux kernel expect that the 101 * interruption map was set as it was done by redboot. 102 */ 103 writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); 104 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); 105 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); 106 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); 107 #endif 108 return 0; 109 } 110