1dd1033e4SGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2dd1033e4SGregory CLEMENT /* 3dd1033e4SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4dd1033e4SGregory CLEMENT */ 5dd1033e4SGregory CLEMENT 6dd1033e4SGregory CLEMENT #include <common.h> 7dd1033e4SGregory CLEMENT 8dd1033e4SGregory CLEMENT #include <asm/io.h> 9dd1033e4SGregory CLEMENT #include <asm/types.h> 10dd1033e4SGregory CLEMENT 11dd1033e4SGregory CLEMENT #include <mach/tlb.h> 12dd1033e4SGregory CLEMENT #include <mach/ddr.h> 13dd1033e4SGregory CLEMENT 14dd1033e4SGregory CLEMENT DECLARE_GLOBAL_DATA_PTR; 15dd1033e4SGregory CLEMENT 16dd1033e4SGregory CLEMENT #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M 17dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_64M 18dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_INVAL 19dd1033e4SGregory CLEMENT #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M 20dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_64M 21dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_RW 22dd1033e4SGregory CLEMENT #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M 23dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_256M 24dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_INVAL 25dd1033e4SGregory CLEMENT #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M 26dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_256M 27dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_RW 28dd1033e4SGregory CLEMENT #else 29dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_512M 30dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_RW 31dd1033e4SGregory CLEMENT #endif 32dd1033e4SGregory CLEMENT 33dd1033e4SGregory CLEMENT /* NOTE: lowlevel_init() function does not have access to the 34dd1033e4SGregory CLEMENT * stack. Thus, all called functions must be inlined, and (any) local 35dd1033e4SGregory CLEMENT * variables must be kept in registers. 36dd1033e4SGregory CLEMENT */ 37dd1033e4SGregory CLEMENT void vcoreiii_tlb_init(void) 38dd1033e4SGregory CLEMENT { 39dd1033e4SGregory CLEMENT register int tlbix = 0; 40dd1033e4SGregory CLEMENT 41dd1033e4SGregory CLEMENT /* 42dd1033e4SGregory CLEMENT * Unlike most of the MIPS based SoCs, the IO register address 43dd1033e4SGregory CLEMENT * are not in KSEG0. The mainline linux kernel built in legacy 44dd1033e4SGregory CLEMENT * mode needs to access some of the registers very early in 45dd1033e4SGregory CLEMENT * the boot and make the assumption that the bootloader has 46dd1033e4SGregory CLEMENT * already configured them, so we have to match this 47dd1033e4SGregory CLEMENT * expectation. 48dd1033e4SGregory CLEMENT */ 49dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, 50dd1033e4SGregory CLEMENT MMU_REGIO_RW); 516bd8231aSGregory CLEMENT #ifdef CONFIG_SOC_LUTON 526bd8231aSGregory CLEMENT create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW, 536bd8231aSGregory CLEMENT MMU_REGIO_RW); 546bd8231aSGregory CLEMENT #endif 55dd1033e4SGregory CLEMENT 56dd1033e4SGregory CLEMENT #if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO 57dd1033e4SGregory CLEMENT /* 58dd1033e4SGregory CLEMENT * If U-Boot is located in NOR then we want to be able to use 59dd1033e4SGregory CLEMENT * the data cache in order to boot in a decent duration 60dd1033e4SGregory CLEMENT */ 61dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, 62dd1033e4SGregory CLEMENT MMU_REGIO_RO_C); 63dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, 64dd1033e4SGregory CLEMENT MMU_REGIO_RO_C); 65dd1033e4SGregory CLEMENT 66dd1033e4SGregory CLEMENT /* 67dd1033e4SGregory CLEMENT * Using cache for RAM also helps to improve boot time. Thanks 68dd1033e4SGregory CLEMENT * to this the time to relocate U-Boot in RAM went from 2.092 69dd1033e4SGregory CLEMENT * secs to 0.104 secs. 70dd1033e4SGregory CLEMENT */ 71dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, 72dd1033e4SGregory CLEMENT MSCC_ATTRIB2); 73dd1033e4SGregory CLEMENT 74dd1033e4SGregory CLEMENT /* Enable caches by clearing the bit ERL, which is set on reset */ 75dd1033e4SGregory CLEMENT write_c0_status(read_c0_status() & ~BIT(2)); 76dd1033e4SGregory CLEMENT #endif /* CONFIG_SYS_TEXT_BASE */ 77dd1033e4SGregory CLEMENT } 78dd1033e4SGregory CLEMENT 79dd1033e4SGregory CLEMENT int mach_cpu_init(void) 80dd1033e4SGregory CLEMENT { 81dd1033e4SGregory CLEMENT /* Speed up NOR flash access */ 826bd8231aSGregory CLEMENT #ifdef CONFIG_SOC_LUTON 836bd8231aSGregory CLEMENT writel(ICPU_PI_MST_CFG_TRISTATE_CTRL + 846bd8231aSGregory CLEMENT ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG); 856bd8231aSGregory CLEMENT 866bd8231aSGregory CLEMENT writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + 876bd8231aSGregory CLEMENT ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 886bd8231aSGregory CLEMENT ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); 896bd8231aSGregory CLEMENT #else 90*e7a0de2cSHoratiu Vultur #ifdef CONFIG_SOC_OCELOT 91dd1033e4SGregory CLEMENT writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 92dd1033e4SGregory CLEMENT ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); 93*e7a0de2cSHoratiu Vultur #endif 94*e7a0de2cSHoratiu Vultur #ifdef CONFIG_SOC_JR2 95*e7a0de2cSHoratiu Vultur writel(ICPU_SPI_MST_CFG_FAST_READ_ENA + 96*e7a0de2cSHoratiu Vultur ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 97*e7a0de2cSHoratiu Vultur ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG); 98*e7a0de2cSHoratiu Vultur #endif 99dd1033e4SGregory CLEMENT /* 100dd1033e4SGregory CLEMENT * Legacy and mainline linux kernel expect that the 101dd1033e4SGregory CLEMENT * interruption map was set as it was done by redboot. 102dd1033e4SGregory CLEMENT */ 103dd1033e4SGregory CLEMENT writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); 104dd1033e4SGregory CLEMENT writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); 105dd1033e4SGregory CLEMENT writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); 106dd1033e4SGregory CLEMENT writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); 1076bd8231aSGregory CLEMENT #endif 108dd1033e4SGregory CLEMENT return 0; 109dd1033e4SGregory CLEMENT } 110