1*dd1033e4SGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*dd1033e4SGregory CLEMENT /* 3*dd1033e4SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4*dd1033e4SGregory CLEMENT */ 5*dd1033e4SGregory CLEMENT 6*dd1033e4SGregory CLEMENT #include <common.h> 7*dd1033e4SGregory CLEMENT 8*dd1033e4SGregory CLEMENT #include <asm/io.h> 9*dd1033e4SGregory CLEMENT #include <asm/types.h> 10*dd1033e4SGregory CLEMENT 11*dd1033e4SGregory CLEMENT #include <mach/tlb.h> 12*dd1033e4SGregory CLEMENT #include <mach/ddr.h> 13*dd1033e4SGregory CLEMENT 14*dd1033e4SGregory CLEMENT DECLARE_GLOBAL_DATA_PTR; 15*dd1033e4SGregory CLEMENT 16*dd1033e4SGregory CLEMENT #if CONFIG_SYS_SDRAM_SIZE <= SZ_64M 17*dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_64M 18*dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_INVAL 19*dd1033e4SGregory CLEMENT #elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M 20*dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_64M 21*dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_RW 22*dd1033e4SGregory CLEMENT #elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M 23*dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_256M 24*dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_INVAL 25*dd1033e4SGregory CLEMENT #elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M 26*dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_256M 27*dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_RW 28*dd1033e4SGregory CLEMENT #else 29*dd1033e4SGregory CLEMENT #define MSCC_RAM_TLB_SIZE SZ_512M 30*dd1033e4SGregory CLEMENT #define MSCC_ATTRIB2 MMU_REGIO_RW 31*dd1033e4SGregory CLEMENT #endif 32*dd1033e4SGregory CLEMENT 33*dd1033e4SGregory CLEMENT /* NOTE: lowlevel_init() function does not have access to the 34*dd1033e4SGregory CLEMENT * stack. Thus, all called functions must be inlined, and (any) local 35*dd1033e4SGregory CLEMENT * variables must be kept in registers. 36*dd1033e4SGregory CLEMENT */ 37*dd1033e4SGregory CLEMENT void vcoreiii_tlb_init(void) 38*dd1033e4SGregory CLEMENT { 39*dd1033e4SGregory CLEMENT register int tlbix = 0; 40*dd1033e4SGregory CLEMENT 41*dd1033e4SGregory CLEMENT /* 42*dd1033e4SGregory CLEMENT * Unlike most of the MIPS based SoCs, the IO register address 43*dd1033e4SGregory CLEMENT * are not in KSEG0. The mainline linux kernel built in legacy 44*dd1033e4SGregory CLEMENT * mode needs to access some of the registers very early in 45*dd1033e4SGregory CLEMENT * the boot and make the assumption that the bootloader has 46*dd1033e4SGregory CLEMENT * already configured them, so we have to match this 47*dd1033e4SGregory CLEMENT * expectation. 48*dd1033e4SGregory CLEMENT */ 49*dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW, 50*dd1033e4SGregory CLEMENT MMU_REGIO_RW); 51*dd1033e4SGregory CLEMENT 52*dd1033e4SGregory CLEMENT #if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO 53*dd1033e4SGregory CLEMENT /* 54*dd1033e4SGregory CLEMENT * If U-Boot is located in NOR then we want to be able to use 55*dd1033e4SGregory CLEMENT * the data cache in order to boot in a decent duration 56*dd1033e4SGregory CLEMENT */ 57*dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C, 58*dd1033e4SGregory CLEMENT MMU_REGIO_RO_C); 59*dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C, 60*dd1033e4SGregory CLEMENT MMU_REGIO_RO_C); 61*dd1033e4SGregory CLEMENT 62*dd1033e4SGregory CLEMENT /* 63*dd1033e4SGregory CLEMENT * Using cache for RAM also helps to improve boot time. Thanks 64*dd1033e4SGregory CLEMENT * to this the time to relocate U-Boot in RAM went from 2.092 65*dd1033e4SGregory CLEMENT * secs to 0.104 secs. 66*dd1033e4SGregory CLEMENT */ 67*dd1033e4SGregory CLEMENT create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, 68*dd1033e4SGregory CLEMENT MSCC_ATTRIB2); 69*dd1033e4SGregory CLEMENT 70*dd1033e4SGregory CLEMENT /* Enable caches by clearing the bit ERL, which is set on reset */ 71*dd1033e4SGregory CLEMENT write_c0_status(read_c0_status() & ~BIT(2)); 72*dd1033e4SGregory CLEMENT #endif /* CONFIG_SYS_TEXT_BASE */ 73*dd1033e4SGregory CLEMENT } 74*dd1033e4SGregory CLEMENT 75*dd1033e4SGregory CLEMENT int mach_cpu_init(void) 76*dd1033e4SGregory CLEMENT { 77*dd1033e4SGregory CLEMENT /* Speed up NOR flash access */ 78*dd1033e4SGregory CLEMENT writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) + 79*dd1033e4SGregory CLEMENT ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); 80*dd1033e4SGregory CLEMENT /* 81*dd1033e4SGregory CLEMENT * Legacy and mainline linux kernel expect that the 82*dd1033e4SGregory CLEMENT * interruption map was set as it was done by redboot. 83*dd1033e4SGregory CLEMENT */ 84*dd1033e4SGregory CLEMENT writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); 85*dd1033e4SGregory CLEMENT writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); 86*dd1033e4SGregory CLEMENT writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); 87*dd1033e4SGregory CLEMENT writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); 88*dd1033e4SGregory CLEMENT 89*dd1033e4SGregory CLEMENT return 0; 90*dd1033e4SGregory CLEMENT } 91