1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * JZ4780 timer
4  *
5  * Copyright (c) 2013 Imagination Technologies
6  * Author: Paul Burton <paul.burton@imgtec.com>
7  */
8 
9 #include <config.h>
10 #include <common.h>
11 #include <div64.h>
12 #include <asm/io.h>
13 #include <asm/mipsregs.h>
14 #include <mach/jz4780.h>
15 
16 #define TCU_TSR		0x1C	/* Timer Stop Register */
17 #define TCU_TSSR	0x2C	/* Timer Stop Set Register */
18 #define TCU_TSCR	0x3C	/* Timer Stop Clear Register */
19 #define TCU_TER		0x10	/* Timer Counter Enable Register */
20 #define TCU_TESR	0x14	/* Timer Counter Enable Set Register */
21 #define TCU_TECR	0x18	/* Timer Counter Enable Clear Register */
22 #define TCU_TFR		0x20	/* Timer Flag Register */
23 #define TCU_TFSR	0x24	/* Timer Flag Set Register */
24 #define TCU_TFCR	0x28	/* Timer Flag Clear Register */
25 #define TCU_TMR		0x30	/* Timer Mask Register */
26 #define TCU_TMSR	0x34	/* Timer Mask Set Register */
27 #define TCU_TMCR	0x38	/* Timer Mask Clear Register */
28 /* n = 0,1,2,3,4,5 */
29 #define TCU_TDFR(n)	(0x40 + (n) * 0x10)	/* Timer Data Full Reg */
30 #define TCU_TDHR(n)	(0x44 + (n) * 0x10)	/* Timer Data Half Reg */
31 #define TCU_TCNT(n)	(0x48 + (n) * 0x10)	/* Timer Counter Reg */
32 #define TCU_TCSR(n)	(0x4C + (n) * 0x10)	/* Timer Control Reg */
33 
34 #define TCU_OSTCNTL	0xe4
35 #define TCU_OSTCNTH	0xe8
36 #define TCU_OSTCSR	0xec
37 #define TCU_OSTCNTHBUF	0xfc
38 
39 /* Register definitions */
40 #define TCU_TCSR_PWM_SD		BIT(9)
41 #define TCU_TCSR_PWM_INITL_HIGH	BIT(8)
42 #define TCU_TCSR_PWM_EN		BIT(7)
43 #define TCU_TCSR_PRESCALE_BIT	3
44 #define TCU_TCSR_PRESCALE_MASK	(0x7 << TCU_TCSR_PRESCALE_BIT)
45 #define TCU_TCSR_PRESCALE1	(0x0 << TCU_TCSR_PRESCALE_BIT)
46 #define TCU_TCSR_PRESCALE4	(0x1 << TCU_TCSR_PRESCALE_BIT)
47 #define TCU_TCSR_PRESCALE16	(0x2 << TCU_TCSR_PRESCALE_BIT)
48 #define TCU_TCSR_PRESCALE64	(0x3 << TCU_TCSR_PRESCALE_BIT)
49 #define TCU_TCSR_PRESCALE256	(0x4 << TCU_TCSR_PRESCALE_BIT)
50 #define TCU_TCSR_PRESCALE1024	(0x5 << TCU_TCSR_PRESCALE_BIT)
51 #define TCU_TCSR_EXT_EN		BIT(2)
52 #define TCU_TCSR_RTC_EN		BIT(1)
53 #define TCU_TCSR_PCK_EN		BIT(0)
54 
55 #define TCU_TER_TCEN5		BIT(5)
56 #define TCU_TER_TCEN4		BIT(4)
57 #define TCU_TER_TCEN3		BIT(3)
58 #define TCU_TER_TCEN2		BIT(2)
59 #define TCU_TER_TCEN1		BIT(1)
60 #define TCU_TER_TCEN0		BIT(0)
61 
62 #define TCU_TESR_TCST5		BIT(5)
63 #define TCU_TESR_TCST4		BIT(4)
64 #define TCU_TESR_TCST3		BIT(3)
65 #define TCU_TESR_TCST2		BIT(2)
66 #define TCU_TESR_TCST1		BIT(1)
67 #define TCU_TESR_TCST0		BIT(0)
68 
69 #define TCU_TECR_TCCL5		BIT(5)
70 #define TCU_TECR_TCCL4		BIT(4)
71 #define TCU_TECR_TCCL3		BIT(3)
72 #define TCU_TECR_TCCL2		BIT(2)
73 #define TCU_TECR_TCCL1		BIT(1)
74 #define TCU_TECR_TCCL0		BIT(0)
75 
76 #define TCU_TFR_HFLAG5		BIT(21)
77 #define TCU_TFR_HFLAG4		BIT(20)
78 #define TCU_TFR_HFLAG3		BIT(19)
79 #define TCU_TFR_HFLAG2		BIT(18)
80 #define TCU_TFR_HFLAG1		BIT(17)
81 #define TCU_TFR_HFLAG0		BIT(16)
82 #define TCU_TFR_FFLAG5		BIT(5)
83 #define TCU_TFR_FFLAG4		BIT(4)
84 #define TCU_TFR_FFLAG3		BIT(3)
85 #define TCU_TFR_FFLAG2		BIT(2)
86 #define TCU_TFR_FFLAG1		BIT(1)
87 #define TCU_TFR_FFLAG0		BIT(0)
88 
89 #define TCU_TFSR_HFLAG5		BIT(21)
90 #define TCU_TFSR_HFLAG4		BIT(20)
91 #define TCU_TFSR_HFLAG3		BIT(19)
92 #define TCU_TFSR_HFLAG2		BIT(18)
93 #define TCU_TFSR_HFLAG1		BIT(17)
94 #define TCU_TFSR_HFLAG0		BIT(16)
95 #define TCU_TFSR_FFLAG5		BIT(5)
96 #define TCU_TFSR_FFLAG4		BIT(4)
97 #define TCU_TFSR_FFLAG3		BIT(3)
98 #define TCU_TFSR_FFLAG2		BIT(2)
99 #define TCU_TFSR_FFLAG1		BIT(1)
100 #define TCU_TFSR_FFLAG0		BIT(0)
101 
102 #define TCU_TFCR_HFLAG5		BIT(21)
103 #define TCU_TFCR_HFLAG4		BIT(20)
104 #define TCU_TFCR_HFLAG3		BIT(19)
105 #define TCU_TFCR_HFLAG2		BIT(18)
106 #define TCU_TFCR_HFLAG1		BIT(17)
107 #define TCU_TFCR_HFLAG0		BIT(16)
108 #define TCU_TFCR_FFLAG5		BIT(5)
109 #define TCU_TFCR_FFLAG4		BIT(4)
110 #define TCU_TFCR_FFLAG3		BIT(3)
111 #define TCU_TFCR_FFLAG2		BIT(2)
112 #define TCU_TFCR_FFLAG1		BIT(1)
113 #define TCU_TFCR_FFLAG0		BIT(0)
114 
115 #define TCU_TMR_HMASK5		BIT(21)
116 #define TCU_TMR_HMASK4		BIT(20)
117 #define TCU_TMR_HMASK3		BIT(19)
118 #define TCU_TMR_HMASK2		BIT(18)
119 #define TCU_TMR_HMASK1		BIT(17)
120 #define TCU_TMR_HMASK0		BIT(16)
121 #define TCU_TMR_FMASK5		BIT(5)
122 #define TCU_TMR_FMASK4		BIT(4)
123 #define TCU_TMR_FMASK3		BIT(3)
124 #define TCU_TMR_FMASK2		BIT(2)
125 #define TCU_TMR_FMASK1		BIT(1)
126 #define TCU_TMR_FMASK0		BIT(0)
127 
128 #define TCU_TMSR_HMST5		BIT(21)
129 #define TCU_TMSR_HMST4		BIT(20)
130 #define TCU_TMSR_HMST3		BIT(19)
131 #define TCU_TMSR_HMST2		BIT(18)
132 #define TCU_TMSR_HMST1		BIT(17)
133 #define TCU_TMSR_HMST0		BIT(16)
134 #define TCU_TMSR_FMST5		BIT(5)
135 #define TCU_TMSR_FMST4		BIT(4)
136 #define TCU_TMSR_FMST3		BIT(3)
137 #define TCU_TMSR_FMST2		BIT(2)
138 #define TCU_TMSR_FMST1		BIT(1)
139 #define TCU_TMSR_FMST0		BIT(0)
140 
141 #define TCU_TMCR_HMCL5		BIT(21)
142 #define TCU_TMCR_HMCL4		BIT(20)
143 #define TCU_TMCR_HMCL3		BIT(19)
144 #define TCU_TMCR_HMCL2		BIT(18)
145 #define TCU_TMCR_HMCL1		BIT(17)
146 #define TCU_TMCR_HMCL0		BIT(16)
147 #define TCU_TMCR_FMCL5		BIT(5)
148 #define TCU_TMCR_FMCL4		BIT(4)
149 #define TCU_TMCR_FMCL3		BIT(3)
150 #define TCU_TMCR_FMCL2		BIT(2)
151 #define TCU_TMCR_FMCL1		BIT(1)
152 #define TCU_TMCR_FMCL0		BIT(0)
153 
154 #define TCU_TSR_WDTS		BIT(16)
155 #define TCU_TSR_STOP5		BIT(5)
156 #define TCU_TSR_STOP4		BIT(4)
157 #define TCU_TSR_STOP3		BIT(3)
158 #define TCU_TSR_STOP2		BIT(2)
159 #define TCU_TSR_STOP1		BIT(1)
160 #define TCU_TSR_STOP0		BIT(0)
161 
162 #define TCU_TSSR_WDTSS		BIT(16)
163 #define TCU_TSSR_STPS5		BIT(5)
164 #define TCU_TSSR_STPS4		BIT(4)
165 #define TCU_TSSR_STPS3		BIT(3)
166 #define TCU_TSSR_STPS2		BIT(2)
167 #define TCU_TSSR_STPS1		BIT(1)
168 #define TCU_TSSR_STPS0		BIT(0)
169 
170 #define TCU_TSSR_WDTSC		BIT(16)
171 #define TCU_TSSR_STPC5		BIT(5)
172 #define TCU_TSSR_STPC4		BIT(4)
173 #define TCU_TSSR_STPC3		BIT(3)
174 #define TCU_TSSR_STPC2		BIT(2)
175 #define TCU_TSSR_STPC1		BIT(1)
176 #define TCU_TSSR_STPC0		BIT(0)
177 
178 #define TER_OSTEN		BIT(15)
179 
180 #define OSTCSR_CNT_MD		BIT(15)
181 #define OSTCSR_SD		BIT(9)
182 #define OSTCSR_PRESCALE_16	(0x2 << 3)
183 #define OSTCSR_EXT_EN		BIT(2)
184 
185 int timer_init(void)
186 {
187 	void __iomem *regs = (void __iomem *)TCU_BASE;
188 
189 	writel(OSTCSR_SD, regs + TCU_OSTCSR);
190 	reset_timer();
191 	writel(OSTCSR_CNT_MD | OSTCSR_EXT_EN | OSTCSR_PRESCALE_16,
192 	       regs + TCU_OSTCSR);
193 	writew(TER_OSTEN, regs + TCU_TESR);
194 	return 0;
195 }
196 
197 void reset_timer(void)
198 {
199 	void __iomem *regs = (void __iomem *)TCU_BASE;
200 
201 	writel(0, regs + TCU_OSTCNTH);
202 	writel(0, regs + TCU_OSTCNTL);
203 }
204 
205 static u64 get_timer64(void)
206 {
207 	void __iomem *regs = (void __iomem *)TCU_BASE;
208 	u32 low = readl(regs + TCU_OSTCNTL);
209 	u32 high = readl(regs + TCU_OSTCNTHBUF);
210 
211 	return ((u64)high << 32) | low;
212 }
213 
214 ulong get_timer(ulong base)
215 {
216 	return lldiv(get_timer64(), 3000) - base;
217 }
218 
219 void __udelay(unsigned long usec)
220 {
221 	/* OST count increments at 3MHz */
222 	u64 end = get_timer64() + ((u64)usec * 3);
223 
224 	while (get_timer64() < end)
225 		;
226 }
227 
228 unsigned long long get_ticks(void)
229 {
230 	return get_timer64();
231 }
232 
233 void jz4780_tcu_wdt_start(void)
234 {
235 	void __iomem *tcu_regs = (void __iomem *)TCU_BASE;
236 
237 	/* Enable WDT clock */
238 	writel(TCU_TSSR_WDTSC, tcu_regs + TCU_TSCR);
239 }
240