1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * JZ4780 DDR initialization 4 * 5 * Copyright (c) 2013 Imagination Technologies 6 * Author: Paul Burton <paul.burton@imgtec.com> 7 * 8 * Based on spl/common/{jz4780_ddr,jz_ddr3_init}.c from X-Boot 9 * Copyright (c) 2006-2013 Ingenic Semiconductor 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <mach/jz4780.h> 15 #include <mach/jz4780_dram.h> 16 17 static const u32 get_mem_clk(void) 18 { 19 const u32 mpll_out = ((u64)JZ4780_SYS_EXTAL * JZ4780_MPLL_M) / 20 (JZ4780_MPLL_N * JZ4780_MPLL_OD); 21 return mpll_out / JZ4780_SYS_MEM_DIV; 22 } 23 24 u32 sdram_size(int cs) 25 { 26 u32 dw = DDR_DW32 ? 4 : 2; 27 u32 banks = DDR_BANK8 ? 8 : 4; 28 u32 size = 0; 29 30 if ((cs == 0) && DDR_CS0EN) { 31 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks; 32 if (DDR_CS1EN && (size > 0x20000000)) 33 size = 0x20000000; 34 } else if ((cs == 1) && DDR_CS1EN) { 35 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks; 36 } 37 38 return size; 39 } 40 41 static void ddr_cfg_init(void) 42 { 43 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; 44 u32 ddrc_cfg, tmp; 45 46 tmp = DDR_CL; 47 if (tmp) 48 tmp--; 49 if (tmp > 4) 50 tmp = 4; 51 52 ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA | 53 DDR_DW32 | DDRC_CFG_MPRT | ((tmp | 0x8) << 2) | 54 ((DDR_ROW - 12) << 11) | ((DDR_COL - 8) << 8) | 55 (DDR_CS0EN << 6) | (DDR_BANK8 << 1) | 56 ((DDR_ROW - 12) << 27) | ((DDR_COL - 8) << 24) | 57 (DDR_CS1EN << 7) | (DDR_BANK8 << 23); 58 59 if (DDR_BL > 4) 60 ddrc_cfg |= BIT(21); 61 62 writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG); 63 } 64 65 static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config) 66 { 67 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; 68 void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET; 69 unsigned int count = 0, i; 70 u32 reg, mask; 71 72 writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), ddr_phy_regs + DDRP_DCR); 73 74 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0); 75 writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1); 76 writel(0, ddr_phy_regs + DDRP_ODTCR); 77 writel(0, ddr_phy_regs + DDRP_MR2); 78 79 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0); 80 writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1); 81 writel(ddr_config->ptr2, ddr_phy_regs + DDRP_PTR2); 82 83 writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0); 84 writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1); 85 writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2); 86 87 writel(DDRP_PGCR_DQSCFG | (7 << DDRP_PGCR_CKEN_BIT) | 88 (2 << DDRP_PGCR_CKDV_BIT) | 89 (DDR_CS0EN | (DDR_CS1EN << 1)) << DDRP_PGCR_RANKEN_BIT | 90 DDRP_PGCR_ZCKSEL_32 | DDRP_PGCR_PDDISDX, 91 ddr_phy_regs + DDRP_PGCR); 92 93 for (i = 0; i < 8; i++) 94 clrbits_le32(ddr_phy_regs + DDRP_DXGCR(i), 0x3 << 9); 95 96 count = 0; 97 mask = DDRP_PGSR_IDONE | DDRP_PGSR_DLDONE | DDRP_PGSR_ZCDONE; 98 for (;;) { 99 reg = readl(ddr_phy_regs + DDRP_PGSR); 100 if ((reg == mask) || (reg == 0x1f)) 101 break; 102 if (count++ == 10000) 103 hang(); 104 } 105 106 /* DQS extension and early set to 1 */ 107 clrsetbits_le32(ddr_phy_regs + DDRP_DSGCR, 0x7E << 4, 0x12 << 4); 108 109 /* 500 pull up and 500 pull down */ 110 clrsetbits_le32(ddr_phy_regs + DDRP_DXCCR, 0xFF << 4, 0xC4 << 4); 111 112 /* Initialise phy */ 113 writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST, 114 ddr_phy_regs + DDRP_PIR); 115 116 count = 0; 117 mask |= DDRP_PGSR_DIDONE; 118 for (;;) { 119 reg = readl(ddr_phy_regs + DDRP_PGSR); 120 if ((reg == mask) || (reg == 0x1f)) 121 break; 122 if (count++ == 20000) 123 hang(); 124 } 125 126 writel(DDRP_PIR_INIT | DDRP_PIR_QSTRN, ddr_phy_regs + DDRP_PIR); 127 128 count = 0; 129 mask |= DDRP_PGSR_DTDONE; 130 for (;;) { 131 reg = readl(ddr_phy_regs + DDRP_PGSR); 132 if (reg == mask) 133 break; 134 if (count++ != 50000) 135 continue; 136 reg &= DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR; 137 if (reg) 138 hang(); 139 count = 0; 140 } 141 142 /* Override impedance */ 143 clrsetbits_le32(ddr_phy_regs + DDRP_ZQXCR0(0), 0x3ff, 144 ((ddr_config->pullup & 0x1f) << DDRP_ZQXCR_PULLUP_IMPE_BIT) | 145 ((ddr_config->pulldn & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPE_BIT) | 146 DDRP_ZQXCR_ZDEN); 147 } 148 149 #define JZBIT(bit) ((bit % 4) * 8) 150 #define JZMASK(bit) (0x1f << JZBIT(bit)) 151 152 static void remap_swap(int a, int b) 153 { 154 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; 155 u32 remmap[2], tmp[2]; 156 157 remmap[0] = readl(ddr_ctl_regs + DDRC_REMMAP(a / 4)); 158 remmap[1] = readl(ddr_ctl_regs + DDRC_REMMAP(b / 4)); 159 160 tmp[0] = (remmap[0] & JZMASK(a)) >> JZBIT(a); 161 tmp[1] = (remmap[1] & JZMASK(b)) >> JZBIT(b); 162 163 remmap[0] &= ~JZMASK(a); 164 remmap[1] &= ~JZMASK(b); 165 166 writel(remmap[0] | (tmp[1] << JZBIT(a)), 167 ddr_ctl_regs + DDRC_REMMAP(a / 4)); 168 writel(remmap[1] | (tmp[0] << JZBIT(b)), 169 ddr_ctl_regs + DDRC_REMMAP(b / 4)); 170 } 171 172 static void mem_remap(void) 173 { 174 u32 start = (DDR_ROW + DDR_COL + (DDR_DW32 ? 4 : 2) / 2) - 12; 175 u32 num = DDR_BANK8 ? 3 : 2; 176 177 if (DDR_CS0EN && DDR_CS1EN) 178 num++; 179 180 for (; num > 0; num--) 181 remap_swap(0 + num - 1, start + num - 1); 182 } 183 184 /* Fetch DRAM config from board file */ 185 __weak const struct jz4780_ddr_config *jz4780_get_ddr_config(void) 186 { 187 return NULL; 188 } 189 190 void sdram_init(void) 191 { 192 const struct jz4780_ddr_config *ddr_config = jz4780_get_ddr_config(); 193 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE; 194 void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET; 195 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 196 u32 mem_clk, tmp, i; 197 u32 mem_base0, mem_base1; 198 u32 mem_mask0, mem_mask1; 199 u32 mem_size0, mem_size1; 200 201 if (!ddr_config) 202 hang(); 203 204 /* Reset DLL in DDR PHY */ 205 writel(0x3, cpm_regs + 0xd0); 206 mdelay(400); 207 writel(0x1, cpm_regs + 0xd0); 208 mdelay(400); 209 210 /* Enter reset */ 211 writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL); 212 213 mem_clk = get_mem_clk(); 214 215 tmp = 1000000000 / mem_clk; 216 if (1000000000 % mem_clk) 217 tmp++; 218 tmp = DDR_tREFI / tmp; 219 tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1; 220 if (tmp > 0xff) 221 tmp = 0xff; 222 if (tmp < 1) 223 tmp = 1; 224 225 writel(0x0, ddr_ctl_regs + DDRC_CTRL); 226 227 writel(0x150000, ddr_phy_regs + DDRP_DTAR); 228 ddr_phy_init(ddr_config); 229 230 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL); 231 writel(0x0, ddr_ctl_regs + DDRC_CTRL); 232 233 ddr_cfg_init(); 234 235 for (i = 0; i < 6; i++) 236 writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i)); 237 238 mem_size0 = sdram_size(0); 239 mem_size1 = sdram_size(1); 240 241 if (!mem_size1 && mem_size0 > 0x20000000) { 242 mem_base0 = 0x0; 243 mem_mask0 = ~(((mem_size0 * 2) >> 24) - 1) & DDRC_MMAP_MASK_MASK; 244 } else { 245 mem_base0 = (DDR_MEM_PHY_BASE >> 24) & 0xff; 246 mem_mask0 = ~((mem_size0 >> 24) - 1) & DDRC_MMAP_MASK_MASK; 247 } 248 249 if (mem_size1) { 250 mem_mask1 = ~((mem_size1 >> 24) - 1) & DDRC_MMAP_MASK_MASK; 251 mem_base1 = ((DDR_MEM_PHY_BASE + mem_size0) >> 24) & 0xff; 252 } else { 253 mem_mask1 = 0; 254 mem_base1 = 0xff; 255 } 256 257 writel(mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0, 258 ddr_ctl_regs + DDRC_MMAP0); 259 writel(mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1, 260 ddr_ctl_regs + DDRC_MMAP1); 261 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL); 262 writel((DDR_CLK_DIV << 1) | DDRC_REFCNT_REF_EN | 263 (tmp << DDRC_REFCNT_CON_BIT), 264 ddr_ctl_regs + DDRC_REFCNT); 265 writel((1 << 15) | (4 << 12) | (1 << 11) | (1 << 8) | (0 << 6) | 266 (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1), 267 ddr_ctl_regs + DDRC_CTRL); 268 mem_remap(); 269 clrbits_le32(ddr_ctl_regs + DDRC_ST, 0x40); 270 } 271