1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/errno.h> 9 #include <asm/io.h> 10 #include <asm/addrspace.h> 11 #include <asm/types.h> 12 #include <mach/ath79.h> 13 #include <mach/ar71xx_regs.h> 14 15 void _machine_restart(void) 16 { 17 void __iomem *base; 18 u32 reg = 0; 19 20 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 21 MAP_NOCACHE); 22 if (soc_is_ar71xx()) 23 reg = AR71XX_RESET_REG_RESET_MODULE; 24 else if (soc_is_ar724x()) 25 reg = AR724X_RESET_REG_RESET_MODULE; 26 else if (soc_is_ar913x()) 27 reg = AR913X_RESET_REG_RESET_MODULE; 28 else if (soc_is_ar933x()) 29 reg = AR933X_RESET_REG_RESET_MODULE; 30 else if (soc_is_ar934x()) 31 reg = AR934X_RESET_REG_RESET_MODULE; 32 else if (soc_is_qca953x()) 33 reg = QCA953X_RESET_REG_RESET_MODULE; 34 else if (soc_is_qca955x()) 35 reg = QCA955X_RESET_REG_RESET_MODULE; 36 else if (soc_is_qca956x()) 37 reg = QCA956X_RESET_REG_RESET_MODULE; 38 else 39 puts("Reset register not defined for this SOC\n"); 40 41 if (reg) 42 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP); 43 44 while (1) 45 /* NOP */; 46 } 47 48 u32 get_bootstrap(void) 49 { 50 void __iomem *base; 51 u32 reg = 0; 52 53 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 54 MAP_NOCACHE); 55 if (soc_is_ar933x()) 56 reg = AR933X_RESET_REG_BOOTSTRAP; 57 else if (soc_is_ar934x()) 58 reg = AR934X_RESET_REG_BOOTSTRAP; 59 else if (soc_is_qca953x()) 60 reg = QCA953X_RESET_REG_BOOTSTRAP; 61 else if (soc_is_qca955x()) 62 reg = QCA955X_RESET_REG_BOOTSTRAP; 63 else if (soc_is_qca956x()) 64 reg = QCA956X_RESET_REG_BOOTSTRAP; 65 else 66 puts("Bootstrap register not defined for this SOC\n"); 67 68 if (reg) 69 return readl(base + reg); 70 71 return 0; 72 } 73 74 static int usb_reset_ar933x(void __iomem *reset_regs) 75 { 76 /* Ungate the USB block */ 77 setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, 78 AR933X_RESET_USBSUS_OVERRIDE); 79 mdelay(1); 80 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, 81 AR933X_RESET_USB_HOST); 82 mdelay(1); 83 clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, 84 AR933X_RESET_USB_PHY); 85 mdelay(1); 86 87 return 0; 88 } 89 90 static int usb_reset_ar934x(void __iomem *reset_regs) 91 { 92 /* Ungate the USB block */ 93 setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, 94 AR934X_RESET_USBSUS_OVERRIDE); 95 mdelay(1); 96 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, 97 AR934X_RESET_USB_PHY); 98 mdelay(1); 99 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, 100 AR934X_RESET_USB_PHY_ANALOG); 101 mdelay(1); 102 clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, 103 AR934X_RESET_USB_HOST); 104 mdelay(1); 105 106 return 0; 107 } 108 109 int ath79_usb_reset(void) 110 { 111 void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE, 112 AR71XX_USB_CTRL_SIZE, 113 MAP_NOCACHE); 114 void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE, 115 AR71XX_RESET_SIZE, 116 MAP_NOCACHE); 117 /* 118 * Turn on the Buff and Desc swap bits. 119 * NOTE: This write into an undocumented register in mandatory to 120 * get the USB controller operational in BigEndian mode. 121 */ 122 writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG); 123 124 if (soc_is_ar933x()) 125 return usb_reset_ar933x(reset_regs); 126 if (soc_is_ar934x()) 127 return usb_reset_ar934x(reset_regs); 128 129 return -EINVAL; 130 } 131