1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/addrspace.h> 10 #include <asm/types.h> 11 #include <mach/ath79.h> 12 #include <mach/ar71xx_regs.h> 13 14 void _machine_restart(void) 15 { 16 void __iomem *base; 17 u32 reg = 0; 18 19 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 20 MAP_NOCACHE); 21 if (soc_is_ar71xx()) 22 reg = AR71XX_RESET_REG_RESET_MODULE; 23 else if (soc_is_ar724x()) 24 reg = AR724X_RESET_REG_RESET_MODULE; 25 else if (soc_is_ar913x()) 26 reg = AR913X_RESET_REG_RESET_MODULE; 27 else if (soc_is_ar933x()) 28 reg = AR933X_RESET_REG_RESET_MODULE; 29 else if (soc_is_ar934x()) 30 reg = AR934X_RESET_REG_RESET_MODULE; 31 else if (soc_is_qca953x()) 32 reg = QCA953X_RESET_REG_RESET_MODULE; 33 else if (soc_is_qca955x()) 34 reg = QCA955X_RESET_REG_RESET_MODULE; 35 else if (soc_is_qca956x()) 36 reg = QCA956X_RESET_REG_RESET_MODULE; 37 else 38 puts("Reset register not defined for this SOC\n"); 39 40 if (reg) 41 setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP); 42 43 while (1) 44 /* NOP */; 45 } 46 47 u32 get_bootstrap(void) 48 { 49 const void __iomem *base; 50 u32 reg = 0; 51 52 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 53 MAP_NOCACHE); 54 if (soc_is_ar933x()) 55 reg = AR933X_RESET_REG_BOOTSTRAP; 56 else if (soc_is_ar934x()) 57 reg = AR934X_RESET_REG_BOOTSTRAP; 58 else if (soc_is_qca953x()) 59 reg = QCA953X_RESET_REG_BOOTSTRAP; 60 else if (soc_is_qca955x()) 61 reg = QCA955X_RESET_REG_BOOTSTRAP; 62 else if (soc_is_qca956x()) 63 reg = QCA956X_RESET_REG_BOOTSTRAP; 64 else 65 puts("Bootstrap register not defined for this SOC\n"); 66 67 if (reg) 68 return readl(base + reg); 69 70 return 0; 71 } 72