1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
21d3d0f1fSWills Wang /*
31d3d0f1fSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
41d3d0f1fSWills Wang */
51d3d0f1fSWills Wang
61d3d0f1fSWills Wang #include <common.h>
71221ce45SMasahiro Yamada #include <linux/errno.h>
81d3d0f1fSWills Wang #include <asm/io.h>
91d3d0f1fSWills Wang #include <asm/addrspace.h>
101d3d0f1fSWills Wang #include <asm/types.h>
111d3d0f1fSWills Wang #include <mach/ath79.h>
121d3d0f1fSWills Wang #include <mach/ar71xx_regs.h>
131d3d0f1fSWills Wang
_machine_restart(void)141d3d0f1fSWills Wang void _machine_restart(void)
151d3d0f1fSWills Wang {
161d3d0f1fSWills Wang void __iomem *base;
171d3d0f1fSWills Wang u32 reg = 0;
181d3d0f1fSWills Wang
191d3d0f1fSWills Wang base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
201d3d0f1fSWills Wang MAP_NOCACHE);
211d3d0f1fSWills Wang if (soc_is_ar71xx())
221d3d0f1fSWills Wang reg = AR71XX_RESET_REG_RESET_MODULE;
231d3d0f1fSWills Wang else if (soc_is_ar724x())
241d3d0f1fSWills Wang reg = AR724X_RESET_REG_RESET_MODULE;
251d3d0f1fSWills Wang else if (soc_is_ar913x())
261d3d0f1fSWills Wang reg = AR913X_RESET_REG_RESET_MODULE;
271d3d0f1fSWills Wang else if (soc_is_ar933x())
281d3d0f1fSWills Wang reg = AR933X_RESET_REG_RESET_MODULE;
291d3d0f1fSWills Wang else if (soc_is_ar934x())
301d3d0f1fSWills Wang reg = AR934X_RESET_REG_RESET_MODULE;
311d3d0f1fSWills Wang else if (soc_is_qca953x())
321d3d0f1fSWills Wang reg = QCA953X_RESET_REG_RESET_MODULE;
331d3d0f1fSWills Wang else if (soc_is_qca955x())
341d3d0f1fSWills Wang reg = QCA955X_RESET_REG_RESET_MODULE;
351d3d0f1fSWills Wang else if (soc_is_qca956x())
361d3d0f1fSWills Wang reg = QCA956X_RESET_REG_RESET_MODULE;
371d3d0f1fSWills Wang else
381d3d0f1fSWills Wang puts("Reset register not defined for this SOC\n");
391d3d0f1fSWills Wang
401d3d0f1fSWills Wang if (reg)
411d3d0f1fSWills Wang setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
421d3d0f1fSWills Wang
431d3d0f1fSWills Wang while (1)
441d3d0f1fSWills Wang /* NOP */;
451d3d0f1fSWills Wang }
461d3d0f1fSWills Wang
ath79_get_bootstrap(void)4737523917SWills Wang u32 ath79_get_bootstrap(void)
481d3d0f1fSWills Wang {
4943a092ffSMarek Vasut void __iomem *base;
501d3d0f1fSWills Wang u32 reg = 0;
511d3d0f1fSWills Wang
521d3d0f1fSWills Wang base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
531d3d0f1fSWills Wang MAP_NOCACHE);
541d3d0f1fSWills Wang if (soc_is_ar933x())
551d3d0f1fSWills Wang reg = AR933X_RESET_REG_BOOTSTRAP;
561d3d0f1fSWills Wang else if (soc_is_ar934x())
571d3d0f1fSWills Wang reg = AR934X_RESET_REG_BOOTSTRAP;
581d3d0f1fSWills Wang else if (soc_is_qca953x())
591d3d0f1fSWills Wang reg = QCA953X_RESET_REG_BOOTSTRAP;
601d3d0f1fSWills Wang else if (soc_is_qca955x())
611d3d0f1fSWills Wang reg = QCA955X_RESET_REG_BOOTSTRAP;
621d3d0f1fSWills Wang else if (soc_is_qca956x())
631d3d0f1fSWills Wang reg = QCA956X_RESET_REG_BOOTSTRAP;
641d3d0f1fSWills Wang else
651d3d0f1fSWills Wang puts("Bootstrap register not defined for this SOC\n");
661d3d0f1fSWills Wang
671d3d0f1fSWills Wang if (reg)
681d3d0f1fSWills Wang return readl(base + reg);
691d3d0f1fSWills Wang
701d3d0f1fSWills Wang return 0;
711d3d0f1fSWills Wang }
726b699742SMarek Vasut
eth_init_ar933x(void)734771bbeeSMarek Vasut static int eth_init_ar933x(void)
744771bbeeSMarek Vasut {
754771bbeeSMarek Vasut void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
764771bbeeSMarek Vasut MAP_NOCACHE);
774771bbeeSMarek Vasut void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
784771bbeeSMarek Vasut MAP_NOCACHE);
794771bbeeSMarek Vasut void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
804771bbeeSMarek Vasut MAP_NOCACHE);
814771bbeeSMarek Vasut const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
824771bbeeSMarek Vasut AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
8342a3f3e6SWills Wang AR933X_RESET_ETH_SWITCH |
8442a3f3e6SWills Wang AR933X_RESET_ETH_SWITCH_ANALOG;
854771bbeeSMarek Vasut
864771bbeeSMarek Vasut /* Clear MDIO slave EN bit. */
874771bbeeSMarek Vasut clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
884771bbeeSMarek Vasut mdelay(10);
894771bbeeSMarek Vasut
904771bbeeSMarek Vasut /* Get Atheros S26 PHY out of reset. */
91ca09e66bSWills Wang clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
924771bbeeSMarek Vasut 0x1f, 0x10);
934771bbeeSMarek Vasut mdelay(10);
944771bbeeSMarek Vasut
954771bbeeSMarek Vasut setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
964771bbeeSMarek Vasut mdelay(10);
974771bbeeSMarek Vasut clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
984771bbeeSMarek Vasut mdelay(10);
994771bbeeSMarek Vasut
1004771bbeeSMarek Vasut /* Configure AR93xx GMAC register. */
1014771bbeeSMarek Vasut clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
1024771bbeeSMarek Vasut AR933X_ETH_CFG_MII_GE0_MASTER |
1034771bbeeSMarek Vasut AR933X_ETH_CFG_MII_GE0_SLAVE,
1044771bbeeSMarek Vasut AR933X_ETH_CFG_MII_GE0_SLAVE);
1054771bbeeSMarek Vasut return 0;
1064771bbeeSMarek Vasut }
1074771bbeeSMarek Vasut
eth_init_ar934x(void)1084771bbeeSMarek Vasut static int eth_init_ar934x(void)
1094771bbeeSMarek Vasut {
1104771bbeeSMarek Vasut void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
1114771bbeeSMarek Vasut MAP_NOCACHE);
1124771bbeeSMarek Vasut void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
1134771bbeeSMarek Vasut MAP_NOCACHE);
1144771bbeeSMarek Vasut void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
1154771bbeeSMarek Vasut MAP_NOCACHE);
1164771bbeeSMarek Vasut const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
1174771bbeeSMarek Vasut AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
1184771bbeeSMarek Vasut AR934X_RESET_ETH_SWITCH_ANALOG;
1194771bbeeSMarek Vasut u32 reg;
1204771bbeeSMarek Vasut
1214771bbeeSMarek Vasut reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
1224771bbeeSMarek Vasut if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
1234771bbeeSMarek Vasut writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
1244771bbeeSMarek Vasut else
1254771bbeeSMarek Vasut writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
1264771bbeeSMarek Vasut writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
1274771bbeeSMarek Vasut
1284771bbeeSMarek Vasut setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
1294771bbeeSMarek Vasut mdelay(1);
1304771bbeeSMarek Vasut clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
1314771bbeeSMarek Vasut mdelay(1);
1324771bbeeSMarek Vasut
1334771bbeeSMarek Vasut /* Configure AR934x GMAC register. */
1344771bbeeSMarek Vasut writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
1354771bbeeSMarek Vasut return 0;
1364771bbeeSMarek Vasut }
1374771bbeeSMarek Vasut
eth_init_qca953x(void)138cdeb68e2SWills Wang static int eth_init_qca953x(void)
139cdeb68e2SWills Wang {
140cdeb68e2SWills Wang void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
141cdeb68e2SWills Wang MAP_NOCACHE);
142cdeb68e2SWills Wang const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
143cdeb68e2SWills Wang QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
144cdeb68e2SWills Wang QCA953X_RESET_ETH_SWITCH_ANALOG |
145cdeb68e2SWills Wang QCA953X_RESET_ETH_SWITCH;
146cdeb68e2SWills Wang
147cdeb68e2SWills Wang setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
148cdeb68e2SWills Wang mdelay(1);
149cdeb68e2SWills Wang clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
150cdeb68e2SWills Wang mdelay(1);
151cdeb68e2SWills Wang
152cdeb68e2SWills Wang return 0;
153cdeb68e2SWills Wang }
154cdeb68e2SWills Wang
ath79_eth_reset(void)1554771bbeeSMarek Vasut int ath79_eth_reset(void)
1564771bbeeSMarek Vasut {
1574771bbeeSMarek Vasut /*
1584771bbeeSMarek Vasut * Un-reset ethernet. DM still doesn't have any notion of reset
1594771bbeeSMarek Vasut * framework, so we do it by hand here.
1604771bbeeSMarek Vasut */
1614771bbeeSMarek Vasut if (soc_is_ar933x())
1624771bbeeSMarek Vasut return eth_init_ar933x();
1634771bbeeSMarek Vasut if (soc_is_ar934x())
1644771bbeeSMarek Vasut return eth_init_ar934x();
165cdeb68e2SWills Wang if (soc_is_qca953x())
166cdeb68e2SWills Wang return eth_init_qca953x();
1674771bbeeSMarek Vasut
1684771bbeeSMarek Vasut return -EINVAL;
1694771bbeeSMarek Vasut }
1704771bbeeSMarek Vasut
usb_reset_ar933x(void __iomem * reset_regs)1716b699742SMarek Vasut static int usb_reset_ar933x(void __iomem *reset_regs)
1726b699742SMarek Vasut {
1736b699742SMarek Vasut /* Ungate the USB block */
1746b699742SMarek Vasut setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
1756b699742SMarek Vasut AR933X_RESET_USBSUS_OVERRIDE);
1766b699742SMarek Vasut mdelay(1);
1776b699742SMarek Vasut clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
1786b699742SMarek Vasut AR933X_RESET_USB_HOST);
1796b699742SMarek Vasut mdelay(1);
1806b699742SMarek Vasut clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
1816b699742SMarek Vasut AR933X_RESET_USB_PHY);
1826b699742SMarek Vasut mdelay(1);
1836b699742SMarek Vasut
1846b699742SMarek Vasut return 0;
1856b699742SMarek Vasut }
1866b699742SMarek Vasut
usb_reset_ar934x(void __iomem * reset_regs)1876b699742SMarek Vasut static int usb_reset_ar934x(void __iomem *reset_regs)
1886b699742SMarek Vasut {
1896b699742SMarek Vasut /* Ungate the USB block */
1906b699742SMarek Vasut setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
1916b699742SMarek Vasut AR934X_RESET_USBSUS_OVERRIDE);
1926b699742SMarek Vasut mdelay(1);
1936b699742SMarek Vasut clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
1946b699742SMarek Vasut AR934X_RESET_USB_PHY);
1956b699742SMarek Vasut mdelay(1);
1966b699742SMarek Vasut clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
1976b699742SMarek Vasut AR934X_RESET_USB_PHY_ANALOG);
1986b699742SMarek Vasut mdelay(1);
1996b699742SMarek Vasut clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
2006b699742SMarek Vasut AR934X_RESET_USB_HOST);
2016b699742SMarek Vasut mdelay(1);
2026b699742SMarek Vasut
2036b699742SMarek Vasut return 0;
2046b699742SMarek Vasut }
2056b699742SMarek Vasut
usb_reset_qca953x(void __iomem * reset_regs)206cdeb68e2SWills Wang static int usb_reset_qca953x(void __iomem *reset_regs)
207cdeb68e2SWills Wang {
208cdeb68e2SWills Wang void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
209cdeb68e2SWills Wang MAP_NOCACHE);
210cdeb68e2SWills Wang
211cdeb68e2SWills Wang clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
212cdeb68e2SWills Wang 0xf00, 0x200);
213cdeb68e2SWills Wang mdelay(10);
214cdeb68e2SWills Wang
215cdeb68e2SWills Wang /* Ungate the USB block */
216cdeb68e2SWills Wang setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
217cdeb68e2SWills Wang QCA953X_RESET_USBSUS_OVERRIDE);
218cdeb68e2SWills Wang mdelay(1);
219cdeb68e2SWills Wang clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
220cdeb68e2SWills Wang QCA953X_RESET_USB_PHY);
221cdeb68e2SWills Wang mdelay(1);
222cdeb68e2SWills Wang clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
223cdeb68e2SWills Wang QCA953X_RESET_USB_PHY_ANALOG);
224cdeb68e2SWills Wang mdelay(1);
225cdeb68e2SWills Wang clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
226cdeb68e2SWills Wang QCA953X_RESET_USB_HOST);
227cdeb68e2SWills Wang mdelay(1);
228cdeb68e2SWills Wang clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
229cdeb68e2SWills Wang QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
230cdeb68e2SWills Wang mdelay(1);
231cdeb68e2SWills Wang
232cdeb68e2SWills Wang return 0;
233cdeb68e2SWills Wang }
234cdeb68e2SWills Wang
ath79_usb_reset(void)2356b699742SMarek Vasut int ath79_usb_reset(void)
2366b699742SMarek Vasut {
2376b699742SMarek Vasut void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
2386b699742SMarek Vasut AR71XX_USB_CTRL_SIZE,
2396b699742SMarek Vasut MAP_NOCACHE);
2406b699742SMarek Vasut void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
2416b699742SMarek Vasut AR71XX_RESET_SIZE,
2426b699742SMarek Vasut MAP_NOCACHE);
2436b699742SMarek Vasut /*
2446b699742SMarek Vasut * Turn on the Buff and Desc swap bits.
2456b699742SMarek Vasut * NOTE: This write into an undocumented register in mandatory to
2466b699742SMarek Vasut * get the USB controller operational in BigEndian mode.
2476b699742SMarek Vasut */
2486b699742SMarek Vasut writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
2496b699742SMarek Vasut
2506b699742SMarek Vasut if (soc_is_ar933x())
2516b699742SMarek Vasut return usb_reset_ar933x(reset_regs);
2526b699742SMarek Vasut if (soc_is_ar934x())
2536b699742SMarek Vasut return usb_reset_ar934x(reset_regs);
254cdeb68e2SWills Wang if (soc_is_qca953x())
255cdeb68e2SWills Wang return usb_reset_qca953x(reset_regs);
2566b699742SMarek Vasut
2576b699742SMarek Vasut return -EINVAL;
2586b699742SMarek Vasut }
259