1/* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * Based on Atheros LSDK/QSDK 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <config.h> 9#include <asm/asm.h> 10#include <asm/regdef.h> 11#include <asm/mipsregs.h> 12#include <asm/addrspace.h> 13#include <mach/ar71xx_regs.h> 14 15#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ 16 (((0x3F & divint) << 10) | \ 17 ((0x1F & refdiv) << 16) | \ 18 ((0x1 & range) << 21) | \ 19 ((0x7 & outdiv) << 23) ) 20 21#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ 22 (((0x3 & (cpudiv - 1)) << 5) | \ 23 ((0x3 & (ddrdiv - 1)) << 10) | \ 24 ((0x3 & (ahbdiv - 1)) << 15) ) 25 26#define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \ 27 QCA953X_##name##_SHIFT) 28 29#define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v) 30#define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v) 31#define DPLL2_PWD QCA953X_SRIF_DPLL2_PWD 32#define MK_DPLL2(ki, kd) (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD) 33 34#define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v) 35#define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v) 36#define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v) 37#define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v) 38#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \ 39 (PLL_CPU_NFRAC(frac) | \ 40 PLL_CPU_NINT(nint) | \ 41 PLL_CPU_REFDIV(ref) | \ 42 PLL_CPU_OUTDIV(outdiv)) 43 44#define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v) 45#define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v) 46#define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v) 47#define PLL_DDR_OUTDIV(v) SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v) 48#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \ 49 (PLL_DDR_NFRAC(frac) | \ 50 PLL_DDR_REFDIV(ref) | \ 51 PLL_DDR_NINT(nint) | \ 52 PLL_DDR_OUTDIV(outdiv) | \ 53 QCA953X_PLL_CONFIG_PWD) 54 55#define PLL_CPU_CONF_VAL MK_PLL_CPU_CONF(0, 26, 1, 0) 56#define PLL_DDR_CONF_VAL MK_PLL_DDR_CONF(0, 15, 1, 0) 57 58#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \ 59 QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \ 60 QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) 61 62#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v) 63#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v) 64#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v) 65#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \ 66 (PLL_CLK_CTRL_CPU_DIV(cpu) | \ 67 PLL_CLK_CTRL_DDR_DIV(ddr) | \ 68 PLL_CLK_CTRL_AHB_DIV(ahb)) 69#define PLL_CLK_CTRL_VAL (MK_PLL_CLK_CTRL(0, 0, 2) | \ 70 PLL_CLK_CTRL_PLL_BYPASS | \ 71 QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \ 72 QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) 73 74#define PLL_DDR_DIT_FRAC_MAX(v) SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v) 75#define PLL_DDR_DIT_FRAC_MIN(v) SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v) 76#define PLL_DDR_DIT_FRAC_STEP(v) SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v) 77#define PLL_DDR_DIT_UPD_CNT(v) SET_FIELD(PLL_DDR_DIT_UPD_CNT, v) 78#define PLL_CPU_DIT_FRAC_MAX(v) SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v) 79#define PLL_CPU_DIT_FRAC_MIN(v) SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v) 80#define PLL_CPU_DIT_FRAC_STEP(v) SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v) 81#define PLL_CPU_DIT_UPD_CNT(v) SET_FIELD(PLL_CPU_DIT_UPD_CNT, v) 82#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \ 83 (QCA953X_PLL_DIT_FRAC_EN | \ 84 PLL_DDR_DIT_FRAC_MAX(max) | \ 85 PLL_DDR_DIT_FRAC_MIN(min) | \ 86 PLL_DDR_DIT_FRAC_STEP(step) | \ 87 PLL_DDR_DIT_UPD_CNT(cnt)) 88#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \ 89 (QCA953X_PLL_DIT_FRAC_EN | \ 90 PLL_CPU_DIT_FRAC_MAX(max) | \ 91 PLL_CPU_DIT_FRAC_MIN(min) | \ 92 PLL_CPU_DIT_FRAC_STEP(step) | \ 93 PLL_CPU_DIT_UPD_CNT(cnt)) 94#define PLL_CPU_DIT_FRAC_VAL MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15) 95#define PLL_DDR_DIT_FRAC_VAL MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15) 96 97 .text 98 .set noreorder 99 100LEAF(lowlevel_init) 101 /* RTC Reset */ 102 li t0, CKSEG1ADDR(AR71XX_RESET_BASE) 103 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0) 104 li t2, 0x08000000 105 or t1, t1, t2 106 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0) 107 nop 108 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0) 109 li t2, 0xf7ffffff 110 and t1, t1, t2 111 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0) 112 nop 113 114 /* RTC Force Wake */ 115 li t0, CKSEG1ADDR(QCA953X_RTC_BASE) 116 li t1, 0x01 117 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0) 118 nop 119 nop 120 121 /* Wait for RTC in on state */ 1221: 123 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0) 124 andi t1, t1, 0x02 125 beqz t1, 1b 126 nop 127 128 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE) 129 li t1, MK_DPLL2(2, 16) 130 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0) 131 sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0) 132 sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0) 133 sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0) 134 135 li t0, CKSEG1ADDR(AR71XX_PLL_BASE) 136 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0) 137 ori t1, PLL_CLK_CTRL_PLL_BYPASS 138 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0) 139 nop 140 141 li t1, PLL_CPU_CONF_VAL 142 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0) 143 nop 144 145 li t1, PLL_DDR_CONF_VAL 146 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0) 147 nop 148 149 li t1, PLL_CLK_CTRL_VAL 150 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0) 151 nop 152 153 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0) 154 li t2, ~QCA953X_PLL_CONFIG_PWD 155 and t1, t1, t2 156 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0) 157 nop 158 159 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0) 160 li t2, ~QCA953X_PLL_CONFIG_PWD 161 and t1, t1, t2 162 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0) 163 nop 164 165 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0) 166 li t2, ~PLL_CLK_CTRL_PLL_BYPASS 167 and t1, t1, t2 168 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0) 169 nop 170 171 li t1, PLL_DDR_DIT_FRAC_VAL 172 sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0) 173 nop 174 175 li t1, PLL_CPU_DIT_FRAC_VAL 176 sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0) 177 nop 178 179 li t0, CKSEG1ADDR(AR71XX_RESET_BASE) 180 lui t1, 0x03fc 181 sw t1, 0xb4(t0) 182 183 nop 184 jr ra 185 nop 186 END(lowlevel_init) 187