1 /*
2  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3  * Based on Atheros LSDK/QSDK
4  *
5  * SPDX-License-Identifier: GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <mach/ar71xx_regs.h>
13 #include <mach/reset.h>
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 #define DDR_CTRL_UPD_EMR3S      BIT(5)
18 #define DDR_CTRL_UPD_EMR2S      BIT(4)
19 #define DDR_CTRL_PRECHARGE      BIT(3)
20 #define DDR_CTRL_AUTO_REFRESH   BIT(2)
21 #define DDR_CTRL_UPD_EMRS       BIT(1)
22 #define DDR_CTRL_UPD_MRS        BIT(0)
23 
24 #define DDR_REFRESH_EN          BIT(14)
25 #define DDR_REFRESH_M           0x3ff
26 #define DDR_REFRESH(x)          ((x) & DDR_REFRESH_M)
27 #define DDR_REFRESH_VAL         (DDR_REFRESH_EN | DDR_REFRESH(312))
28 
29 #define DDR_TRAS_S              0
30 #define DDR_TRAS_M              0x1f
31 #define DDR_TRAS(x)             (((x) & DDR_TRAS_M) << DDR_TRAS_S)
32 #define DDR_TRCD_M              0xf
33 #define DDR_TRCD_S              5
34 #define DDR_TRCD(x)             (((x) & DDR_TRCD_M) << DDR_TRCD_S)
35 #define DDR_TRP_M               0xf
36 #define DDR_TRP_S               9
37 #define DDR_TRP(x)              (((x) & DDR_TRP_M) << DDR_TRP_S)
38 #define DDR_TRRD_M              0xf
39 #define DDR_TRRD_S              13
40 #define DDR_TRRD(x)             (((x) & DDR_TRRD_M) << DDR_TRRD_S)
41 #define DDR_TRFC_M              0x7f
42 #define DDR_TRFC_S              17
43 #define DDR_TRFC(x)             (((x) & DDR_TRFC_M) << DDR_TRFC_S)
44 #define DDR_TMRD_M              0xf
45 #define DDR_TMRD_S              23
46 #define DDR_TMRD(x)             (((x) & DDR_TMRD_M) << DDR_TMRD_S)
47 #define DDR_CAS_L_M             0x17
48 #define DDR_CAS_L_S             27
49 #define DDR_CAS_L(x)            (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
50 #define DDR_OPEN                BIT(30)
51 #define DDR1_CONF_REG_VAL       (DDR_TRAS(16) | DDR_TRCD(6) | \
52 				 DDR_TRP(6) | DDR_TRRD(4) | \
53 				 DDR_TRFC(7) | DDR_TMRD(5) | \
54 				 DDR_CAS_L(7) | DDR_OPEN)
55 #define DDR2_CONF_REG_VAL       (DDR_TRAS(27) | DDR_TRCD(9) | \
56 				 DDR_TRP(9) | DDR_TRRD(7) | \
57 				 DDR_TRFC(21) | DDR_TMRD(15) | \
58 				 DDR_CAS_L(17) | DDR_OPEN)
59 
60 #define DDR_BURST_LEN_S         0
61 #define DDR_BURST_LEN_M         0xf
62 #define DDR_BURST_LEN(x)        ((x) << DDR_BURST_LEN_S)
63 #define DDR_BURST_TYPE          BIT(4)
64 #define DDR_CNTL_OE_EN          BIT(5)
65 #define DDR_PHASE_SEL           BIT(6)
66 #define DDR_CKE                 BIT(7)
67 #define DDR_TWR_S               8
68 #define DDR_TWR_M               0xf
69 #define DDR_TWR(x)              (((x) & DDR_TWR_M) << DDR_TWR_S)
70 #define DDR_TRTW_S              12
71 #define DDR_TRTW_M              0x1f
72 #define DDR_TRTW(x)             (((x) & DDR_TRTW_M) << DDR_TRTW_S)
73 #define DDR_TRTP_S              17
74 #define DDR_TRTP_M              0xf
75 #define DDR_TRTP(x)             (((x) & DDR_TRTP_M) << DDR_TRTP_S)
76 #define DDR_TWTR_S              21
77 #define DDR_TWTR_M              0x1f
78 #define DDR_TWTR(x)             (((x) & DDR_TWTR_M) << DDR_TWTR_S)
79 #define DDR_G_OPEN_L_S          26
80 #define DDR_G_OPEN_L_M          0xf
81 #define DDR_G_OPEN_L(x)         ((x) << DDR_G_OPEN_L_S)
82 #define DDR_HALF_WIDTH_LOW      BIT(31)
83 #define DDR1_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
84 				 DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
85 				 DDR_TRTP(8) | DDR_TWTR(14) | \
86 				 DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
87 #define DDR2_CONF2_REG_VAL      (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
88 				 DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
89 				 DDR_TRTP(9) | DDR_TWTR(21) | \
90 				 DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
91 
92 #define DDR_TWR_MSB             BIT(3)
93 #define DDR_TRAS_MSB            BIT(2)
94 #define DDR_TRFC_MSB_M          0x3
95 #define DDR_TRFC_MSB(x)         (x)
96 #define DDR1_CONF3_REG_VAL      0
97 #define DDR2_CONF3_REG_VAL      (DDR_TWR_MSB | DDR_TRFC_MSB(2))
98 
99 #define DDR_CTL_SRAM_TSEL       BIT(30)
100 #define DDR_CTL_SRAM_GE0_SYNC   BIT(20)
101 #define DDR_CTL_SRAM_GE1_SYNC   BIT(19)
102 #define DDR_CTL_SRAM_USB_SYNC   BIT(18)
103 #define DDR_CTL_SRAM_PCIE_SYNC  BIT(17)
104 #define DDR_CTL_SRAM_WMAC_SYNC  BIT(16)
105 #define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
106 #define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
107 #define DDR_CTL_PAD_DDR2_SEL    BIT(6)
108 #define DDR_CTL_HALF_WIDTH      BIT(1)
109 #define DDR_CTL_CONFIG_VAL      (DDR_CTL_SRAM_TSEL | \
110 				 DDR_CTL_SRAM_GE0_SYNC | \
111 				 DDR_CTL_SRAM_GE1_SYNC | \
112 				 DDR_CTL_SRAM_USB_SYNC | \
113 				 DDR_CTL_SRAM_PCIE_SYNC | \
114 				 DDR_CTL_SRAM_WMAC_SYNC | \
115 				 DDR_CTL_HALF_WIDTH)
116 
117 #define DDR_BURST_GE0_MAX_BL_S  0
118 #define DDR_BURST_GE0_MAX_BL_M  0xf
119 #define DDR_BURST_GE0_MAX_BL(x) \
120 	(((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
121 #define DDR_BURST_GE1_MAX_BL_S  4
122 #define DDR_BURST_GE1_MAX_BL_M  0xf
123 #define DDR_BURST_GE1_MAX_BL(x) \
124 	(((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
125 #define DDR_BURST_PCIE_MAX_BL_S 8
126 #define DDR_BURST_PCIE_MAX_BL_M 0xf
127 #define DDR_BURST_PCIE_MAX_BL(x) \
128 	(((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
129 #define DDR_BURST_USB_MAX_BL_S  12
130 #define DDR_BURST_USB_MAX_BL_M  0xf
131 #define DDR_BURST_USB_MAX_BL(x) \
132 	(((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
133 #define DDR_BURST_CPU_MAX_BL_S  16
134 #define DDR_BURST_CPU_MAX_BL_M  0xf
135 #define DDR_BURST_CPU_MAX_BL(x) \
136 	(((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
137 #define DDR_BURST_RD_MAX_BL_S   20
138 #define DDR_BURST_RD_MAX_BL_M   0xf
139 #define DDR_BURST_RD_MAX_BL(x) \
140 	(((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
141 #define DDR_BURST_WR_MAX_BL_S   24
142 #define DDR_BURST_WR_MAX_BL_M   0xf
143 #define DDR_BURST_WR_MAX_BL(x) \
144 	(((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
145 #define DDR_BURST_RWP_MASK_EN_S 28
146 #define DDR_BURST_RWP_MASK_EN_M 0x3
147 #define DDR_BURST_RWP_MASK_EN(x) \
148 	(((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
149 #define DDR_BURST_CPU_PRI_BE    BIT(30)
150 #define DDR_BURST_CPU_PRI       BIT(31)
151 #define DDR_BURST_VAL           (DDR_BURST_CPU_PRI_BE | \
152 				 DDR_BURST_RWP_MASK_EN(3) | \
153 				 DDR_BURST_WR_MAX_BL(4) | \
154 				 DDR_BURST_RD_MAX_BL(4) | \
155 				 DDR_BURST_CPU_MAX_BL(4) | \
156 				 DDR_BURST_USB_MAX_BL(4) | \
157 				 DDR_BURST_PCIE_MAX_BL(4) | \
158 				 DDR_BURST_GE1_MAX_BL(4) | \
159 				 DDR_BURST_GE0_MAX_BL(4))
160 
161 #define DDR_BURST_WMAC_MAX_BL_S 0
162 #define DDR_BURST_WMAC_MAX_BL_M 0xf
163 #define DDR_BURST_WMAC_MAX_BL(x) \
164 	(((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
165 #define DDR_BURST2_VAL          DDR_BURST_WMAC_MAX_BL(4)
166 
167 #define DDR2_CONF_TWL_S         10
168 #define DDR2_CONF_TWL_M         0xf
169 #define DDR2_CONF_TWL(x) \
170 	(((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
171 #define DDR2_CONF_ODT           BIT(9)
172 #define DDR2_CONF_TFAW_S        2
173 #define DDR2_CONF_TFAW_M        0x3f
174 #define DDR2_CONF_TFAW(x) \
175 	(((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
176 #define DDR2_CONF_EN            BIT(0)
177 #define DDR2_CONF_VAL           (DDR2_CONF_TWL(5) | \
178 				 DDR2_CONF_TFAW(31) | \
179 				 DDR2_CONF_ODT | \
180 				 DDR2_CONF_EN)
181 
182 #define DDR1_EXT_MODE_VAL       0
183 #define DDR2_EXT_MODE_VAL       0x402
184 #define DDR2_EXT_MODE_OCD_VAL   0x782
185 #define DDR1_MODE_DLL_VAL       0x133
186 #define DDR2_MODE_DLL_VAL       0x143
187 #define DDR1_MODE_VAL           0x33
188 #define DDR2_MODE_VAL           0x43
189 #define DDR1_TAP_VAL            0x20
190 #define DDR2_TAP_VAL            0x10
191 
192 #define DDR_REG_BIST_MASK_ADDR_0        0x2c
193 #define DDR_REG_BIST_MASK_ADDR_1        0x30
194 #define DDR_REG_BIST_MASK_AHB_GE0_0     0x34
195 #define DDR_REG_BIST_COMP_AHB_GE0_0     0x38
196 #define DDR_REG_BIST_MASK_AHB_GE1_0     0x3c
197 #define DDR_REG_BIST_COMP_AHB_GE1_0     0x40
198 #define DDR_REG_BIST_COMP_ADDR_0        0x64
199 #define DDR_REG_BIST_COMP_ADDR_1        0x68
200 #define DDR_REG_BIST_MASK_AHB_GE0_1     0x6c
201 #define DDR_REG_BIST_COMP_AHB_GE0_1     0x70
202 #define DDR_REG_BIST_MASK_AHB_GE1_1     0x74
203 #define DDR_REG_BIST_COMP_AHB_GE1_1     0x78
204 #define DDR_REG_BIST                    0x11c
205 #define DDR_REG_BIST_STATUS             0x120
206 
207 #define DDR_BIST_COMP_CNT_S     1
208 #define DDR_BIST_COMP_CNT_M     0xff
209 #define DDR_BIST_COMP_CNT(x) \
210 	(((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
211 #define DDR_BIST_COMP_CNT_MASK \
212 	(DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
213 #define DDR_BIST_TEST_START     BIT(0)
214 #define DDR_BIST_STATUS_DONE    BIT(0)
215 
216 /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
217 #define DDR_BIST_MASK_ADDR_VAL  0xfa5de83f
218 
219 #define DDR_TAP_MAGIC_VAL       0xaa55aa55
220 #define DDR_TAP_MAX_VAL         0x40
221 
222 void ddr_init(void)
223 {
224 	void __iomem *regs;
225 	u32 val;
226 
227 	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
228 			   MAP_NOCACHE);
229 	val = get_bootstrap();
230 	if (val & QCA953X_BOOTSTRAP_DDR1) {
231 		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
232 		udelay(10);
233 
234 		/* For 16-bit DDR */
235 		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
236 		udelay(100);
237 
238 		/* Burst size */
239 		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
240 		udelay(100);
241 		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
242 		udelay(100);
243 
244 		/* AHB maximum timeout */
245 		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
246 		udelay(100);
247 
248 		/* DRAM timing */
249 		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
250 		udelay(100);
251 		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
252 		udelay(100);
253 		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
254 		udelay(100);
255 
256 		/* Precharge All */
257 		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
258 		udelay(100);
259 
260 		/* ODT disable, Full strength, Enable DLL */
261 		writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
262 		udelay(100);
263 
264 		/* Update Extended Mode Register Set (EMRS) */
265 		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
266 		udelay(100);
267 
268 		/* Reset DLL, CAS Latency 3, Burst Length 8 */
269 		writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
270 		udelay(100);
271 
272 		/* Update Mode Register Set (MRS) */
273 		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
274 		udelay(100);
275 
276 		/* Precharge All */
277 		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
278 		udelay(100);
279 
280 		/* Auto Refresh */
281 		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
282 		udelay(100);
283 		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
284 		udelay(100);
285 
286 		/* Normal DLL, CAS Latency 3, Burst Length 8 */
287 		writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
288 		udelay(100);
289 
290 		/* Update Mode Register Set (MRS) */
291 		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
292 		udelay(100);
293 
294 		/* Refresh time control */
295 		writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
296 		udelay(100);
297 
298 		/* DQS 0 Tap Control */
299 		writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
300 
301 		/* DQS 1 Tap Control */
302 		writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
303 	} else {
304 		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
305 		udelay(10);
306 		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
307 		udelay(10);
308 		writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
309 		       regs + QCA953X_DDR_REG_CTL_CONF);
310 		udelay(10);
311 
312 		/* For 16-bit DDR */
313 		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
314 		udelay(100);
315 
316 		/* Burst size */
317 		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
318 		udelay(100);
319 		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
320 		udelay(100);
321 
322 		/* AHB maximum timeout */
323 		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
324 		udelay(100);
325 
326 		/* DRAM timing */
327 		writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
328 		udelay(100);
329 		writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
330 		udelay(100);
331 		writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
332 		udelay(100);
333 
334 		/* Enable DDR2 */
335 		writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
336 		udelay(100);
337 
338 		/* Precharge All */
339 		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
340 		udelay(100);
341 
342 		/* Update Extended Mode Register 2 Set (EMR2S) */
343 		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
344 		udelay(100);
345 
346 		/* Update Extended Mode Register 3 Set (EMR3S) */
347 		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
348 		udelay(100);
349 
350 		/* 150 ohm, Reduced strength, Enable DLL */
351 		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
352 		udelay(100);
353 
354 		/* Update Extended Mode Register Set (EMRS) */
355 		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
356 		udelay(100);
357 
358 		/* Reset DLL, CAS Latency 4, Burst Length 8 */
359 		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
360 		udelay(100);
361 
362 		/* Update Mode Register Set (MRS) */
363 		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
364 		udelay(100);
365 
366 		/* Precharge All */
367 		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
368 		udelay(100);
369 
370 		/* Auto Refresh */
371 		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
372 		udelay(100);
373 		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
374 		udelay(100);
375 
376 		/* Normal DLL, CAS Latency 4, Burst Length 8 */
377 		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
378 		udelay(100);
379 
380 		/* Mode Register Set (MRS) */
381 		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
382 		udelay(100);
383 
384 		/* Enable OCD, Enable DLL, Reduced Drive Strength */
385 		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
386 		udelay(100);
387 
388 		/* Update Extended Mode Register Set (EMRS) */
389 		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
390 		udelay(100);
391 
392 		/* OCD diable, Enable DLL, Reduced Drive Strength */
393 		writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
394 		udelay(100);
395 
396 		/* Update Extended Mode Register Set (EMRS) */
397 		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
398 		udelay(100);
399 
400 		/* Refresh time control */
401 		writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
402 		udelay(100);
403 
404 		/* DQS 0 Tap Control */
405 		writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
406 
407 		/* DQS 1 Tap Control */
408 		writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
409 	}
410 }
411 
412 void ddr_tap_tuning(void)
413 {
414 	void __iomem *regs;
415 	u32 val, pass, tap, cnt, tap_val, last, first;
416 
417 	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
418 			   MAP_NOCACHE);
419 
420 	tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
421 	first = DDR_TAP_MAGIC_VAL;
422 	last = 0;
423 	cnt = 0;
424 	tap = 0;
425 
426 	do {
427 		writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
428 		writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
429 
430 		writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
431 		writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
432 		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
433 		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
434 		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
435 		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
436 		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
437 		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
438 		writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
439 		writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
440 
441 		/* Start BIST test */
442 		writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
443 
444 		do {
445 			val = readl(regs + DDR_REG_BIST_STATUS);
446 		} while (!(val & DDR_BIST_STATUS_DONE));
447 
448 		/* Stop BIST test */
449 		writel(0, regs + DDR_REG_BIST);
450 
451 		pass = val & DDR_BIST_COMP_CNT_MASK;
452 		pass ^= DDR_BIST_COMP_CNT(8);
453 		if (!pass) {
454 			if (first != DDR_TAP_MAGIC_VAL) {
455 				last = tap;
456 			} else  {
457 				first = tap;
458 				last = tap;
459 			}
460 			cnt++;
461 		}
462 		tap++;
463 	} while (tap < DDR_TAP_MAX_VAL);
464 
465 	if (cnt) {
466 		tap_val = (first + last) / 2;
467 		tap_val %= DDR_TAP_MAX_VAL;
468 	}
469 
470 	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
471 	writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
472 }
473