1 /* 2 * Atheros AR71XX/AR724X/AR913X SoC register definitions 3 * 4 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __ASM_MACH_AR71XX_REGS_H 13 #define __ASM_MACH_AR71XX_REGS_H 14 15 #ifndef __ASSEMBLY__ 16 #include <linux/bitops.h> 17 #else 18 #ifndef BIT 19 #define BIT(nr) (1 << (nr)) 20 #endif 21 #endif 22 23 #define AR71XX_APB_BASE 0x18000000 24 #define AR71XX_GE0_BASE 0x19000000 25 #define AR71XX_GE0_SIZE 0x10000 26 #define AR71XX_GE1_BASE 0x1a000000 27 #define AR71XX_GE1_SIZE 0x10000 28 #define AR71XX_EHCI_BASE 0x1b000000 29 #define AR71XX_EHCI_SIZE 0x1000 30 #define AR71XX_OHCI_BASE 0x1c000000 31 #define AR71XX_OHCI_SIZE 0x1000 32 #define AR71XX_SPI_BASE 0x1f000000 33 #define AR71XX_SPI_SIZE 0x01000000 34 35 #define AR71XX_DDR_CTRL_BASE \ 36 (AR71XX_APB_BASE + 0x00000000) 37 #define AR71XX_DDR_CTRL_SIZE 0x100 38 #define AR71XX_UART_BASE \ 39 (AR71XX_APB_BASE + 0x00020000) 40 #define AR71XX_UART_SIZE 0x100 41 #define AR71XX_USB_CTRL_BASE \ 42 (AR71XX_APB_BASE + 0x00030000) 43 #define AR71XX_USB_CTRL_SIZE 0x100 44 #define AR71XX_GPIO_BASE \ 45 (AR71XX_APB_BASE + 0x00040000) 46 #define AR71XX_GPIO_SIZE 0x100 47 #define AR71XX_PLL_BASE \ 48 (AR71XX_APB_BASE + 0x00050000) 49 #define AR71XX_PLL_SIZE 0x100 50 #define AR71XX_RESET_BASE \ 51 (AR71XX_APB_BASE + 0x00060000) 52 #define AR71XX_RESET_SIZE 0x100 53 #define AR71XX_MII_BASE \ 54 (AR71XX_APB_BASE + 0x00070000) 55 #define AR71XX_MII_SIZE 0x100 56 57 #define AR71XX_PCI_MEM_BASE 0x10000000 58 #define AR71XX_PCI_MEM_SIZE 0x07000000 59 60 #define AR71XX_PCI_WIN0_OFFS 0x10000000 61 #define AR71XX_PCI_WIN1_OFFS 0x11000000 62 #define AR71XX_PCI_WIN2_OFFS 0x12000000 63 #define AR71XX_PCI_WIN3_OFFS 0x13000000 64 #define AR71XX_PCI_WIN4_OFFS 0x14000000 65 #define AR71XX_PCI_WIN5_OFFS 0x15000000 66 #define AR71XX_PCI_WIN6_OFFS 0x16000000 67 #define AR71XX_PCI_WIN7_OFFS 0x07000000 68 69 #define AR71XX_PCI_CFG_BASE \ 70 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) 71 #define AR71XX_PCI_CFG_SIZE 0x100 72 73 #define AR7240_USB_CTRL_BASE \ 74 (AR71XX_APB_BASE + 0x00030000) 75 #define AR7240_USB_CTRL_SIZE 0x100 76 #define AR7240_OHCI_BASE 0x1b000000 77 #define AR7240_OHCI_SIZE 0x1000 78 79 #define AR724X_PCI_MEM_BASE 0x10000000 80 #define AR724X_PCI_MEM_SIZE 0x04000000 81 82 #define AR724X_PCI_CFG_BASE 0x14000000 83 #define AR724X_PCI_CFG_SIZE 0x1000 84 #define AR724X_PCI_CRP_BASE \ 85 (AR71XX_APB_BASE + 0x000c0000) 86 #define AR724X_PCI_CRP_SIZE 0x1000 87 #define AR724X_PCI_CTRL_BASE \ 88 (AR71XX_APB_BASE + 0x000f0000) 89 #define AR724X_PCI_CTRL_SIZE 0x100 90 91 #define AR724X_EHCI_BASE 0x1b000000 92 #define AR724X_EHCI_SIZE 0x1000 93 94 #define AR913X_EHCI_BASE 0x1b000000 95 #define AR913X_EHCI_SIZE 0x1000 96 #define AR913X_WMAC_BASE \ 97 (AR71XX_APB_BASE + 0x000C0000) 98 #define AR913X_WMAC_SIZE 0x30000 99 100 #define AR933X_UART_BASE \ 101 (AR71XX_APB_BASE + 0x00020000) 102 #define AR933X_UART_SIZE 0x14 103 #define AR933X_GMAC_BASE \ 104 (AR71XX_APB_BASE + 0x00070000) 105 #define AR933X_GMAC_SIZE 0x04 106 #define AR933X_WMAC_BASE \ 107 (AR71XX_APB_BASE + 0x00100000) 108 #define AR933X_WMAC_SIZE 0x20000 109 #define AR933X_RTC_BASE \ 110 (AR71XX_APB_BASE + 0x00107000) 111 #define AR933X_RTC_SIZE 0x1000 112 #define AR933X_EHCI_BASE 0x1b000000 113 #define AR933X_EHCI_SIZE 0x1000 114 #define AR933X_SRIF_BASE \ 115 (AR71XX_APB_BASE + 0x00116000) 116 #define AR933X_SRIF_SIZE 0x1000 117 118 #define AR934X_GMAC_BASE \ 119 (AR71XX_APB_BASE + 0x00070000) 120 #define AR934X_GMAC_SIZE 0x14 121 #define AR934X_WMAC_BASE \ 122 (AR71XX_APB_BASE + 0x00100000) 123 #define AR934X_WMAC_SIZE 0x20000 124 #define AR934X_EHCI_BASE 0x1b000000 125 #define AR934X_EHCI_SIZE 0x200 126 #define AR934X_NFC_BASE 0x1b000200 127 #define AR934X_NFC_SIZE 0xb8 128 #define AR934X_SRIF_BASE \ 129 (AR71XX_APB_BASE + 0x00116000) 130 #define AR934X_SRIF_SIZE 0x1000 131 132 #define QCA953X_GMAC_BASE \ 133 (AR71XX_APB_BASE + 0x00070000) 134 #define QCA953X_GMAC_SIZE 0x14 135 #define QCA953X_WMAC_BASE \ 136 (AR71XX_APB_BASE + 0x00100000) 137 #define QCA953X_WMAC_SIZE 0x20000 138 #define QCA953X_RTC_BASE \ 139 (AR71XX_APB_BASE + 0x00107000) 140 #define QCA953X_RTC_SIZE 0x1000 141 #define QCA953X_EHCI_BASE 0x1b000000 142 #define QCA953X_EHCI_SIZE 0x200 143 #define QCA953X_SRIF_BASE \ 144 (AR71XX_APB_BASE + 0x00116000) 145 #define QCA953X_SRIF_SIZE 0x1000 146 147 #define QCA953X_PCI_CFG_BASE0 0x14000000 148 #define QCA953X_PCI_CTRL_BASE0 \ 149 (AR71XX_APB_BASE + 0x000f0000) 150 #define QCA953X_PCI_CRP_BASE0 \ 151 (AR71XX_APB_BASE + 0x000c0000) 152 #define QCA953X_PCI_MEM_BASE0 0x10000000 153 #define QCA953X_PCI_MEM_SIZE 0x02000000 154 155 #define QCA955X_PCI_MEM_BASE0 0x10000000 156 #define QCA955X_PCI_MEM_BASE1 0x12000000 157 #define QCA955X_PCI_MEM_SIZE 0x02000000 158 #define QCA955X_PCI_CFG_BASE0 0x14000000 159 #define QCA955X_PCI_CFG_BASE1 0x16000000 160 #define QCA955X_PCI_CFG_SIZE 0x1000 161 #define QCA955X_PCI_CRP_BASE0 \ 162 (AR71XX_APB_BASE + 0x000c0000) 163 #define QCA955X_PCI_CRP_BASE1 \ 164 (AR71XX_APB_BASE + 0x00250000) 165 #define QCA955X_PCI_CRP_SIZE 0x1000 166 #define QCA955X_PCI_CTRL_BASE0 \ 167 (AR71XX_APB_BASE + 0x000f0000) 168 #define QCA955X_PCI_CTRL_BASE1 \ 169 (AR71XX_APB_BASE + 0x00280000) 170 #define QCA955X_PCI_CTRL_SIZE 0x100 171 172 #define QCA955X_GMAC_BASE \ 173 (AR71XX_APB_BASE + 0x00070000) 174 #define QCA955X_GMAC_SIZE 0x40 175 #define QCA955X_WMAC_BASE \ 176 (AR71XX_APB_BASE + 0x00100000) 177 #define QCA955X_WMAC_SIZE 0x20000 178 #define QCA955X_EHCI0_BASE 0x1b000000 179 #define QCA955X_EHCI1_BASE 0x1b400000 180 #define QCA955X_EHCI_SIZE 0x1000 181 #define QCA955X_NFC_BASE 0x1b800200 182 #define QCA955X_NFC_SIZE 0xb8 183 184 #define QCA956X_PCI_MEM_BASE1 0x12000000 185 #define QCA956X_PCI_MEM_SIZE 0x02000000 186 #define QCA956X_PCI_CFG_BASE1 0x16000000 187 #define QCA956X_PCI_CFG_SIZE 0x1000 188 #define QCA956X_PCI_CRP_BASE1 \ 189 (AR71XX_APB_BASE + 0x00250000) 190 #define QCA956X_PCI_CRP_SIZE 0x1000 191 #define QCA956X_PCI_CTRL_BASE1 \ 192 (AR71XX_APB_BASE + 0x00280000) 193 #define QCA956X_PCI_CTRL_SIZE 0x100 194 195 #define QCA956X_WMAC_BASE \ 196 (AR71XX_APB_BASE + 0x00100000) 197 #define QCA956X_WMAC_SIZE 0x20000 198 #define QCA956X_EHCI0_BASE 0x1b000000 199 #define QCA956X_EHCI1_BASE 0x1b400000 200 #define QCA956X_EHCI_SIZE 0x200 201 #define QCA956X_GMAC_BASE \ 202 (AR71XX_APB_BASE + 0x00070000) 203 #define QCA956X_GMAC_SIZE 0x64 204 205 /* 206 * DDR_CTRL block 207 */ 208 #define AR71XX_DDR_REG_CONFIG 0x00 209 #define AR71XX_DDR_REG_CONFIG2 0x04 210 #define AR71XX_DDR_REG_MODE 0x08 211 #define AR71XX_DDR_REG_EMR 0x0c 212 #define AR71XX_DDR_REG_CONTROL 0x10 213 #define AR71XX_DDR_REG_REFRESH 0x14 214 #define AR71XX_DDR_REG_RD_CYCLE 0x18 215 #define AR71XX_DDR_REG_TAP_CTRL0 0x1c 216 #define AR71XX_DDR_REG_TAP_CTRL1 0x20 217 218 #define AR71XX_DDR_REG_PCI_WIN0 0x7c 219 #define AR71XX_DDR_REG_PCI_WIN1 0x80 220 #define AR71XX_DDR_REG_PCI_WIN2 0x84 221 #define AR71XX_DDR_REG_PCI_WIN3 0x88 222 #define AR71XX_DDR_REG_PCI_WIN4 0x8c 223 #define AR71XX_DDR_REG_PCI_WIN5 0x90 224 #define AR71XX_DDR_REG_PCI_WIN6 0x94 225 #define AR71XX_DDR_REG_PCI_WIN7 0x98 226 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c 227 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 228 #define AR71XX_DDR_REG_FLUSH_USB 0xa4 229 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 230 231 #define AR724X_DDR_REG_FLUSH_GE0 0x7c 232 #define AR724X_DDR_REG_FLUSH_GE1 0x80 233 #define AR724X_DDR_REG_FLUSH_USB 0x84 234 #define AR724X_DDR_REG_FLUSH_PCIE 0x88 235 236 #define AR913X_DDR_REG_FLUSH_GE0 0x7c 237 #define AR913X_DDR_REG_FLUSH_GE1 0x80 238 #define AR913X_DDR_REG_FLUSH_USB 0x84 239 #define AR913X_DDR_REG_FLUSH_WMAC 0x88 240 241 #define AR933X_DDR_REG_FLUSH_GE0 0x7c 242 #define AR933X_DDR_REG_FLUSH_GE1 0x80 243 #define AR933X_DDR_REG_FLUSH_USB 0x84 244 #define AR933X_DDR_REG_FLUSH_WMAC 0x88 245 #define AR933X_DDR_REG_DDR2_CONFIG 0x8c 246 #define AR933X_DDR_REG_EMR2 0x90 247 #define AR933X_DDR_REG_EMR3 0x94 248 #define AR933X_DDR_REG_BURST 0x98 249 #define AR933X_DDR_REG_TIMEOUT_MAX 0x9c 250 #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c 251 #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c 252 253 #define AR934X_DDR_REG_FLUSH_GE0 0x9c 254 #define AR934X_DDR_REG_FLUSH_GE1 0xa0 255 #define AR934X_DDR_REG_FLUSH_USB 0xa4 256 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 257 #define AR934X_DDR_REG_FLUSH_WMAC 0xac 258 259 #define QCA953X_DDR_REG_FLUSH_GE0 0x9c 260 #define QCA953X_DDR_REG_FLUSH_GE1 0xa0 261 #define QCA953X_DDR_REG_FLUSH_USB 0xa4 262 #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 263 #define QCA953X_DDR_REG_FLUSH_WMAC 0xac 264 #define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 265 #define QCA953X_DDR_REG_BURST 0xc4 266 #define QCA953X_DDR_REG_BURST2 0xc8 267 #define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc 268 #define QCA953X_DDR_REG_CTL_CONF 0x108 269 #define QCA953X_DDR_REG_CONFIG3 0x15c 270 271 /* 272 * PLL block 273 */ 274 #define AR71XX_PLL_REG_CPU_CONFIG 0x00 275 #define AR71XX_PLL_REG_SEC_CONFIG 0x04 276 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 277 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 278 279 #define AR71XX_PLL_DIV_SHIFT 3 280 #define AR71XX_PLL_DIV_MASK 0x1f 281 #define AR71XX_CPU_DIV_SHIFT 16 282 #define AR71XX_CPU_DIV_MASK 0x3 283 #define AR71XX_DDR_DIV_SHIFT 18 284 #define AR71XX_DDR_DIV_MASK 0x3 285 #define AR71XX_AHB_DIV_SHIFT 20 286 #define AR71XX_AHB_DIV_MASK 0x7 287 288 #define AR71XX_ETH0_PLL_SHIFT 17 289 #define AR71XX_ETH1_PLL_SHIFT 19 290 291 #define AR724X_PLL_REG_CPU_CONFIG 0x00 292 #define AR724X_PLL_REG_PCIE_CONFIG 0x18 293 294 #define AR724X_PLL_DIV_SHIFT 0 295 #define AR724X_PLL_DIV_MASK 0x3ff 296 #define AR724X_PLL_REF_DIV_SHIFT 10 297 #define AR724X_PLL_REF_DIV_MASK 0xf 298 #define AR724X_AHB_DIV_SHIFT 19 299 #define AR724X_AHB_DIV_MASK 0x1 300 #define AR724X_DDR_DIV_SHIFT 22 301 #define AR724X_DDR_DIV_MASK 0x3 302 303 #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c 304 305 #define AR913X_PLL_REG_CPU_CONFIG 0x00 306 #define AR913X_PLL_REG_ETH_CONFIG 0x04 307 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 308 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 309 310 #define AR913X_PLL_DIV_SHIFT 0 311 #define AR913X_PLL_DIV_MASK 0x3ff 312 #define AR913X_DDR_DIV_SHIFT 22 313 #define AR913X_DDR_DIV_MASK 0x3 314 #define AR913X_AHB_DIV_SHIFT 19 315 #define AR913X_AHB_DIV_MASK 0x1 316 317 #define AR913X_ETH0_PLL_SHIFT 20 318 #define AR913X_ETH1_PLL_SHIFT 22 319 320 #define AR933X_PLL_CPU_CONFIG_REG 0x00 321 #define AR933X_PLL_CLK_CTRL_REG 0x08 322 #define AR933X_PLL_DITHER_FRAC_REG 0x10 323 324 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 325 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 326 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 327 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 328 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 329 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 330 331 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) 332 #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 333 #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 334 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 335 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 336 #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 337 #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 338 339 #define AR934X_PLL_CPU_CONFIG_REG 0x00 340 #define AR934X_PLL_DDR_CONFIG_REG 0x04 341 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 342 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 343 #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c 344 345 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 346 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 347 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 348 #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 349 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 350 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 351 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 352 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 353 354 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 355 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 356 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 357 #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 358 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 359 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 360 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 361 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 362 363 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 364 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 365 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 366 #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 367 #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 368 #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 369 #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 370 #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 371 #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 372 #define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 373 #define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 374 #define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 375 376 #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) 377 378 #define QCA953X_PLL_CPU_CONFIG_REG 0x00 379 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 380 #define QCA953X_PLL_CLK_CTRL_REG 0x08 381 #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 382 #define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c 383 #define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 384 #define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 385 386 #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 387 #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 388 #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 389 #define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f 390 #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 391 #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 392 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 393 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 394 395 #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 396 #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 397 #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 398 #define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f 399 #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 400 #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 401 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 402 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 403 404 #define QCA953X_PLL_CONFIG_PWD BIT(30) 405 406 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 407 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 408 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 409 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 410 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 411 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 412 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 413 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 414 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 415 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 416 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 417 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 418 419 #define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 420 #define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 421 #define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 422 #define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 423 #define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 424 #define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 425 #define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 426 #define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 427 428 #define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 429 #define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 430 #define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 431 #define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 432 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 433 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 434 #define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 435 #define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 436 437 #define QCA953X_PLL_DIT_FRAC_EN BIT(31) 438 439 #define QCA955X_PLL_CPU_CONFIG_REG 0x00 440 #define QCA955X_PLL_DDR_CONFIG_REG 0x04 441 #define QCA955X_PLL_CLK_CTRL_REG 0x08 442 #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 443 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 444 445 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 446 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 447 #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 448 #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 449 #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 450 #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 451 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 452 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 453 454 #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 455 #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 456 #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 457 #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 458 #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 459 #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 460 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 461 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 462 463 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 464 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 465 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 466 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 467 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 468 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 469 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 470 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 471 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 472 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 473 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 474 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 475 476 #define QCA956X_PLL_CPU_CONFIG_REG 0x00 477 #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 478 #define QCA956X_PLL_DDR_CONFIG_REG 0x08 479 #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c 480 #define QCA956X_PLL_CLK_CTRL_REG 0x10 481 482 #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 483 #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 484 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 485 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 486 487 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 488 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f 489 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 490 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff 491 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 492 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff 493 494 #define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 495 #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 496 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 497 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 498 499 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 500 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f 501 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 502 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff 503 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 504 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff 505 506 #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 507 #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 508 #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 509 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 510 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 511 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 512 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 513 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 514 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 515 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) 516 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) 517 #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 518 519 /* 520 * USB_CONFIG block 521 */ 522 #define AR71XX_USB_CTRL_REG_FLADJ 0x00 523 #define AR71XX_USB_CTRL_REG_CONFIG 0x04 524 525 /* 526 * RESET block 527 */ 528 #define AR71XX_RESET_REG_TIMER 0x00 529 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 530 #define AR71XX_RESET_REG_WDOG_CTRL 0x08 531 #define AR71XX_RESET_REG_WDOG 0x0c 532 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 533 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 534 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 535 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 536 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 537 #define AR71XX_RESET_REG_RESET_MODULE 0x24 538 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c 539 #define AR71XX_RESET_REG_PERFC0 0x30 540 #define AR71XX_RESET_REG_PERFC1 0x34 541 #define AR71XX_RESET_REG_REV_ID 0x90 542 543 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 544 #define AR913X_RESET_REG_RESET_MODULE 0x1c 545 #define AR913X_RESET_REG_PERF_CTRL 0x20 546 #define AR913X_RESET_REG_PERFC0 0x24 547 #define AR913X_RESET_REG_PERFC1 0x28 548 549 #define AR724X_RESET_REG_RESET_MODULE 0x1c 550 551 #define AR933X_RESET_REG_RESET_MODULE 0x1c 552 #define AR933X_RESET_REG_BOOTSTRAP 0xac 553 554 #define AR934X_RESET_REG_RESET_MODULE 0x1c 555 #define AR934X_RESET_REG_BOOTSTRAP 0xb0 556 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 557 558 #define QCA953X_RESET_REG_RESET_MODULE 0x1c 559 #define QCA953X_RESET_REG_BOOTSTRAP 0xb0 560 #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 561 562 #define QCA955X_RESET_REG_RESET_MODULE 0x1c 563 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 564 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac 565 566 #define QCA956X_RESET_REG_RESET_MODULE 0x1c 567 #define QCA956X_RESET_REG_BOOTSTRAP 0xb0 568 #define QCA956X_RESET_REG_EXT_INT_STATUS 0xac 569 570 #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) 571 #define MISC_INT_ETHSW BIT(12) 572 #define MISC_INT_TIMER4 BIT(10) 573 #define MISC_INT_TIMER3 BIT(9) 574 #define MISC_INT_TIMER2 BIT(8) 575 #define MISC_INT_DMA BIT(7) 576 #define MISC_INT_OHCI BIT(6) 577 #define MISC_INT_PERFC BIT(5) 578 #define MISC_INT_WDOG BIT(4) 579 #define MISC_INT_UART BIT(3) 580 #define MISC_INT_GPIO BIT(2) 581 #define MISC_INT_ERROR BIT(1) 582 #define MISC_INT_TIMER BIT(0) 583 584 #define AR71XX_RESET_EXTERNAL BIT(28) 585 #define AR71XX_RESET_FULL_CHIP BIT(24) 586 #define AR71XX_RESET_CPU_NMI BIT(21) 587 #define AR71XX_RESET_CPU_COLD BIT(20) 588 #define AR71XX_RESET_DMA BIT(19) 589 #define AR71XX_RESET_SLIC BIT(18) 590 #define AR71XX_RESET_STEREO BIT(17) 591 #define AR71XX_RESET_DDR BIT(16) 592 #define AR71XX_RESET_GE1_MAC BIT(13) 593 #define AR71XX_RESET_GE1_PHY BIT(12) 594 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 595 #define AR71XX_RESET_GE0_MAC BIT(9) 596 #define AR71XX_RESET_GE0_PHY BIT(8) 597 #define AR71XX_RESET_USB_OHCI_DLL BIT(6) 598 #define AR71XX_RESET_USB_HOST BIT(5) 599 #define AR71XX_RESET_USB_PHY BIT(4) 600 #define AR71XX_RESET_PCI_BUS BIT(1) 601 #define AR71XX_RESET_PCI_CORE BIT(0) 602 603 #define AR7240_RESET_USB_HOST BIT(5) 604 #define AR7240_RESET_OHCI_DLL BIT(3) 605 606 #define AR724X_RESET_GE1_MDIO BIT(23) 607 #define AR724X_RESET_GE0_MDIO BIT(22) 608 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 609 #define AR724X_RESET_PCIE_PHY BIT(7) 610 #define AR724X_RESET_PCIE BIT(6) 611 #define AR724X_RESET_USB_HOST BIT(5) 612 #define AR724X_RESET_USB_PHY BIT(4) 613 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 614 615 #define AR913X_RESET_AMBA2WMAC BIT(22) 616 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 617 #define AR913X_RESET_USB_HOST BIT(5) 618 #define AR913X_RESET_USB_PHY BIT(4) 619 620 #define AR933X_RESET_GE1_MDIO BIT(23) 621 #define AR933X_RESET_GE0_MDIO BIT(22) 622 #define AR933X_RESET_GE1_MAC BIT(13) 623 #define AR933X_RESET_WMAC BIT(11) 624 #define AR933X_RESET_GE0_MAC BIT(9) 625 #define AR933X_RESET_ETH_SWITCH BIT(8) 626 #define AR933X_RESET_USB_HOST BIT(5) 627 #define AR933X_RESET_USB_PHY BIT(4) 628 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 629 630 #define AR934X_RESET_HOST BIT(31) 631 #define AR934X_RESET_SLIC BIT(30) 632 #define AR934X_RESET_HDMA BIT(29) 633 #define AR934X_RESET_EXTERNAL BIT(28) 634 #define AR934X_RESET_RTC BIT(27) 635 #define AR934X_RESET_PCIE_EP_INT BIT(26) 636 #define AR934X_RESET_CHKSUM_ACC BIT(25) 637 #define AR934X_RESET_FULL_CHIP BIT(24) 638 #define AR934X_RESET_GE1_MDIO BIT(23) 639 #define AR934X_RESET_GE0_MDIO BIT(22) 640 #define AR934X_RESET_CPU_NMI BIT(21) 641 #define AR934X_RESET_CPU_COLD BIT(20) 642 #define AR934X_RESET_HOST_RESET_INT BIT(19) 643 #define AR934X_RESET_PCIE_EP BIT(18) 644 #define AR934X_RESET_UART1 BIT(17) 645 #define AR934X_RESET_DDR BIT(16) 646 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 647 #define AR934X_RESET_NANDF BIT(14) 648 #define AR934X_RESET_GE1_MAC BIT(13) 649 #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) 650 #define AR934X_RESET_USB_PHY_ANALOG BIT(11) 651 #define AR934X_RESET_HOST_DMA_INT BIT(10) 652 #define AR934X_RESET_GE0_MAC BIT(9) 653 #define AR934X_RESET_ETH_SWITCH BIT(8) 654 #define AR934X_RESET_PCIE_PHY BIT(7) 655 #define AR934X_RESET_PCIE BIT(6) 656 #define AR934X_RESET_USB_HOST BIT(5) 657 #define AR934X_RESET_USB_PHY BIT(4) 658 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 659 #define AR934X_RESET_LUT BIT(2) 660 #define AR934X_RESET_MBOX BIT(1) 661 #define AR934X_RESET_I2S BIT(0) 662 663 #define QCA953X_RESET_USB_EXT_PWR BIT(29) 664 #define QCA953X_RESET_EXTERNAL BIT(28) 665 #define QCA953X_RESET_RTC BIT(27) 666 #define QCA953X_RESET_FULL_CHIP BIT(24) 667 #define QCA953X_RESET_GE1_MDIO BIT(23) 668 #define QCA953X_RESET_GE0_MDIO BIT(22) 669 #define QCA953X_RESET_CPU_NMI BIT(21) 670 #define QCA953X_RESET_CPU_COLD BIT(20) 671 #define QCA953X_RESET_DDR BIT(16) 672 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 673 #define QCA953X_RESET_GE1_MAC BIT(13) 674 #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) 675 #define QCA953X_RESET_USB_PHY_ANALOG BIT(11) 676 #define QCA953X_RESET_GE0_MAC BIT(9) 677 #define QCA953X_RESET_ETH_SWITCH BIT(8) 678 #define QCA953X_RESET_PCIE_PHY BIT(7) 679 #define QCA953X_RESET_PCIE BIT(6) 680 #define QCA953X_RESET_USB_HOST BIT(5) 681 #define QCA953X_RESET_USB_PHY BIT(4) 682 #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) 683 684 #define QCA955X_RESET_HOST BIT(31) 685 #define QCA955X_RESET_SLIC BIT(30) 686 #define QCA955X_RESET_HDMA BIT(29) 687 #define QCA955X_RESET_EXTERNAL BIT(28) 688 #define QCA955X_RESET_RTC BIT(27) 689 #define QCA955X_RESET_PCIE_EP_INT BIT(26) 690 #define QCA955X_RESET_CHKSUM_ACC BIT(25) 691 #define QCA955X_RESET_FULL_CHIP BIT(24) 692 #define QCA955X_RESET_GE1_MDIO BIT(23) 693 #define QCA955X_RESET_GE0_MDIO BIT(22) 694 #define QCA955X_RESET_CPU_NMI BIT(21) 695 #define QCA955X_RESET_CPU_COLD BIT(20) 696 #define QCA955X_RESET_HOST_RESET_INT BIT(19) 697 #define QCA955X_RESET_PCIE_EP BIT(18) 698 #define QCA955X_RESET_UART1 BIT(17) 699 #define QCA955X_RESET_DDR BIT(16) 700 #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 701 #define QCA955X_RESET_NANDF BIT(14) 702 #define QCA955X_RESET_GE1_MAC BIT(13) 703 #define QCA955X_RESET_SGMII_ANALOG BIT(12) 704 #define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 705 #define QCA955X_RESET_HOST_DMA_INT BIT(10) 706 #define QCA955X_RESET_GE0_MAC BIT(9) 707 #define QCA955X_RESET_SGMII BIT(8) 708 #define QCA955X_RESET_PCIE_PHY BIT(7) 709 #define QCA955X_RESET_PCIE BIT(6) 710 #define QCA955X_RESET_USB_HOST BIT(5) 711 #define QCA955X_RESET_USB_PHY BIT(4) 712 #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 713 #define QCA955X_RESET_LUT BIT(2) 714 #define QCA955X_RESET_MBOX BIT(1) 715 #define QCA955X_RESET_I2S BIT(0) 716 717 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) 718 #define AR933X_BOOTSTRAP_DDR2 BIT(13) 719 #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) 720 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 721 722 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 723 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 724 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 725 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 726 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 727 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 728 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 729 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 730 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 731 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 732 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 733 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 734 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 735 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 736 #define AR934X_BOOTSTRAP_DDR1 BIT(0) 737 738 #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) 739 #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) 740 #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) 741 #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) 742 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 743 #define QCA953X_BOOTSTRAP_DDR1 BIT(0) 744 745 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 746 747 #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) 748 749 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 750 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 751 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 752 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 753 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 754 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 755 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 756 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 757 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 758 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 759 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 760 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 761 762 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 763 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 764 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 765 AR934X_PCIE_WMAC_INT_PCIE_RC3) 766 767 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 768 #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) 769 #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 770 #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 771 #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) 772 #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 773 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 774 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 775 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 776 #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ 777 (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ 778 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) 779 780 #define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ 781 (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ 782 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ 783 QCA953X_PCIE_WMAC_INT_PCIE_RC3) 784 785 #define QCA955X_EXT_INT_WMAC_MISC BIT(0) 786 #define QCA955X_EXT_INT_WMAC_TX BIT(1) 787 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 788 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 789 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 790 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 791 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 792 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 793 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 794 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 795 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 796 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 797 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 798 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 799 #define QCA955X_EXT_INT_USB1 BIT(24) 800 #define QCA955X_EXT_INT_USB2 BIT(28) 801 802 #define QCA955X_EXT_INT_WMAC_ALL \ 803 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 804 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 805 806 #define QCA955X_EXT_INT_PCIE_RC1_ALL \ 807 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 808 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 809 QCA955X_EXT_INT_PCIE_RC1_INT3) 810 811 #define QCA955X_EXT_INT_PCIE_RC2_ALL \ 812 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 813 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 814 QCA955X_EXT_INT_PCIE_RC2_INT3) 815 816 #define QCA956X_EXT_INT_WMAC_MISC BIT(0) 817 #define QCA956X_EXT_INT_WMAC_TX BIT(1) 818 #define QCA956X_EXT_INT_WMAC_RXLP BIT(2) 819 #define QCA956X_EXT_INT_WMAC_RXHP BIT(3) 820 #define QCA956X_EXT_INT_PCIE_RC1 BIT(4) 821 #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) 822 #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) 823 #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) 824 #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) 825 #define QCA956X_EXT_INT_PCIE_RC2 BIT(12) 826 #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) 827 #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) 828 #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) 829 #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) 830 #define QCA956X_EXT_INT_USB1 BIT(24) 831 #define QCA956X_EXT_INT_USB2 BIT(28) 832 833 #define QCA956X_EXT_INT_WMAC_ALL \ 834 (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ 835 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) 836 837 #define QCA956X_EXT_INT_PCIE_RC1_ALL \ 838 (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ 839 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ 840 QCA956X_EXT_INT_PCIE_RC1_INT3) 841 842 #define QCA956X_EXT_INT_PCIE_RC2_ALL \ 843 (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ 844 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ 845 QCA956X_EXT_INT_PCIE_RC2_INT3) 846 847 #define REV_ID_MAJOR_MASK 0xfff0 848 #define REV_ID_MAJOR_AR71XX 0x00a0 849 #define REV_ID_MAJOR_AR913X 0x00b0 850 #define REV_ID_MAJOR_AR7240 0x00c0 851 #define REV_ID_MAJOR_AR7241 0x0100 852 #define REV_ID_MAJOR_AR7242 0x1100 853 #define REV_ID_MAJOR_AR9330 0x0110 854 #define REV_ID_MAJOR_AR9331 0x1110 855 #define REV_ID_MAJOR_AR9341 0x0120 856 #define REV_ID_MAJOR_AR9342 0x1120 857 #define REV_ID_MAJOR_AR9344 0x2120 858 #define REV_ID_MAJOR_QCA9533 0x0140 859 #define REV_ID_MAJOR_QCA9533_V2 0x0160 860 #define REV_ID_MAJOR_QCA9556 0x0130 861 #define REV_ID_MAJOR_QCA9558 0x1130 862 #define REV_ID_MAJOR_TP9343 0x0150 863 #define REV_ID_MAJOR_QCA9561 0x1150 864 865 #define AR71XX_REV_ID_MINOR_MASK 0x3 866 #define AR71XX_REV_ID_MINOR_AR7130 0x0 867 #define AR71XX_REV_ID_MINOR_AR7141 0x1 868 #define AR71XX_REV_ID_MINOR_AR7161 0x2 869 #define AR913X_REV_ID_MINOR_AR9130 0x0 870 #define AR913X_REV_ID_MINOR_AR9132 0x1 871 872 #define AR71XX_REV_ID_REVISION_MASK 0x3 873 #define AR71XX_REV_ID_REVISION_SHIFT 2 874 #define AR71XX_REV_ID_REVISION2_MASK 0xf 875 876 /* 877 * RTC block 878 */ 879 #define AR933X_RTC_REG_RESET 0x40 880 #define AR933X_RTC_REG_STATUS 0x44 881 #define AR933X_RTC_REG_DERIVED 0x48 882 #define AR933X_RTC_REG_FORCE_WAKE 0x4c 883 #define AR933X_RTC_REG_INT_CAUSE 0x50 884 #define AR933X_RTC_REG_CAUSE_CLR 0x50 885 #define AR933X_RTC_REG_INT_ENABLE 0x54 886 #define AR933X_RTC_REG_INT_MASKE 0x58 887 888 #define QCA953X_RTC_REG_SYNC_RESET 0x40 889 #define QCA953X_RTC_REG_SYNC_STATUS 0x44 890 891 /* 892 * SPI block 893 */ 894 #define AR71XX_SPI_REG_FS 0x00 895 #define AR71XX_SPI_REG_CTRL 0x04 896 #define AR71XX_SPI_REG_IOC 0x08 897 #define AR71XX_SPI_REG_RDS 0x0c 898 899 #define AR71XX_SPI_FS_GPIO BIT(0) 900 901 #define AR71XX_SPI_CTRL_RD BIT(6) 902 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f 903 904 #define AR71XX_SPI_IOC_DO BIT(0) 905 #define AR71XX_SPI_IOC_CLK BIT(8) 906 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 907 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 908 #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 909 #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 910 #define AR71XX_SPI_IOC_CS_ALL \ 911 (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) 912 913 /* 914 * GPIO block 915 */ 916 #define AR71XX_GPIO_REG_OE 0x00 917 #define AR71XX_GPIO_REG_IN 0x04 918 #define AR71XX_GPIO_REG_OUT 0x08 919 #define AR71XX_GPIO_REG_SET 0x0c 920 #define AR71XX_GPIO_REG_CLEAR 0x10 921 #define AR71XX_GPIO_REG_INT_MODE 0x14 922 #define AR71XX_GPIO_REG_INT_TYPE 0x18 923 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 924 #define AR71XX_GPIO_REG_INT_PENDING 0x20 925 #define AR71XX_GPIO_REG_INT_ENABLE 0x24 926 #define AR71XX_GPIO_REG_FUNC 0x28 927 #define AR933X_GPIO_REG_FUNC 0x30 928 929 #define AR934X_GPIO_REG_OUT_FUNC0 0x2c 930 #define AR934X_GPIO_REG_OUT_FUNC1 0x30 931 #define AR934X_GPIO_REG_OUT_FUNC2 0x34 932 #define AR934X_GPIO_REG_OUT_FUNC3 0x38 933 #define AR934X_GPIO_REG_OUT_FUNC4 0x3c 934 #define AR934X_GPIO_REG_OUT_FUNC5 0x40 935 #define AR934X_GPIO_REG_FUNC 0x6c 936 937 #define QCA953X_GPIO_REG_OUT_FUNC0 0x2c 938 #define QCA953X_GPIO_REG_OUT_FUNC1 0x30 939 #define QCA953X_GPIO_REG_OUT_FUNC2 0x34 940 #define QCA953X_GPIO_REG_OUT_FUNC3 0x38 941 #define QCA953X_GPIO_REG_OUT_FUNC4 0x3c 942 #define QCA953X_GPIO_REG_IN_ENABLE0 0x44 943 #define QCA953X_GPIO_REG_FUNC 0x6c 944 945 #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c 946 #define QCA955X_GPIO_REG_OUT_FUNC1 0x30 947 #define QCA955X_GPIO_REG_OUT_FUNC2 0x34 948 #define QCA955X_GPIO_REG_OUT_FUNC3 0x38 949 #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c 950 #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 951 #define QCA955X_GPIO_REG_FUNC 0x6c 952 953 #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c 954 #define QCA956X_GPIO_REG_OUT_FUNC1 0x30 955 #define QCA956X_GPIO_REG_OUT_FUNC2 0x34 956 #define QCA956X_GPIO_REG_OUT_FUNC3 0x38 957 #define QCA956X_GPIO_REG_OUT_FUNC4 0x3c 958 #define QCA956X_GPIO_REG_OUT_FUNC5 0x40 959 #define QCA956X_GPIO_REG_IN_ENABLE0 0x44 960 #define QCA956X_GPIO_REG_IN_ENABLE3 0x50 961 #define QCA956X_GPIO_REG_FUNC 0x6c 962 963 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) 964 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) 965 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) 966 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) 967 #define AR71XX_GPIO_FUNC_UART_EN BIT(8) 968 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) 969 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) 970 971 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) 972 #define AR724X_GPIO_FUNC_SPI_EN BIT(18) 973 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 974 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 975 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) 976 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) 977 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) 978 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) 979 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) 980 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 981 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 982 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 983 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 984 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 985 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 986 #define AR724X_GPIO_FUNC_UART_EN BIT(1) 987 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) 988 989 #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) 990 #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) 991 #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) 992 #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) 993 #define AR913X_GPIO_FUNC_I2S1_EN BIT(18) 994 #define AR913X_GPIO_FUNC_I2S0_EN BIT(17) 995 #define AR913X_GPIO_FUNC_SLIC_EN BIT(16) 996 #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) 997 #define AR913X_GPIO_FUNC_UART_EN BIT(8) 998 #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) 999 1000 #define AR933X_GPIO(x) BIT(x) 1001 #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) 1002 #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) 1003 #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) 1004 #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) 1005 #define AR933X_GPIO_FUNC_I2SO_EN BIT(26) 1006 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) 1007 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) 1008 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) 1009 #define AR933X_GPIO_FUNC_SPI_EN BIT(18) 1010 #define AR933X_GPIO_FUNC_RES_TRUE BIT(15) 1011 #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 1012 #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 1013 #define AR933X_GPIO_FUNC_XLNA_EN BIT(12) 1014 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 1015 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 1016 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 1017 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 1018 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 1019 #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 1020 #define AR933X_GPIO_FUNC_UART_EN BIT(1) 1021 #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) 1022 1023 #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) 1024 #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) 1025 #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) 1026 #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) 1027 #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) 1028 #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) 1029 #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) 1030 #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) 1031 #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) 1032 1033 #define AR934X_GPIO_OUT_GPIO 0 1034 #define AR934X_GPIO_OUT_SPI_CS1 7 1035 #define AR934X_GPIO_OUT_LED_LINK0 41 1036 #define AR934X_GPIO_OUT_LED_LINK1 42 1037 #define AR934X_GPIO_OUT_LED_LINK2 43 1038 #define AR934X_GPIO_OUT_LED_LINK3 44 1039 #define AR934X_GPIO_OUT_LED_LINK4 45 1040 #define AR934X_GPIO_OUT_EXT_LNA0 46 1041 #define AR934X_GPIO_OUT_EXT_LNA1 47 1042 1043 #define QCA953X_GPIO(x) BIT(x) 1044 #define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) 1045 #define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 1046 #define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 1047 #define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 1048 #define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 1049 #define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 1050 #define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 1051 #define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 1052 #define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 1053 #define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 1054 #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 1055 #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 1056 1057 #define QCA953X_GPIO_IN_MUX_UART0_SIN 9 1058 #define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 1059 1060 #define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 1061 #define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 1062 1063 #define AR71XX_GPIO_COUNT 16 1064 #define AR7240_GPIO_COUNT 18 1065 #define AR7241_GPIO_COUNT 20 1066 #define AR913X_GPIO_COUNT 22 1067 #define AR933X_GPIO_COUNT 30 1068 #define AR934X_GPIO_COUNT 23 1069 #define QCA953X_GPIO_COUNT 18 1070 #define QCA955X_GPIO_COUNT 24 1071 #define QCA956X_GPIO_COUNT 23 1072 1073 /* 1074 * SRIF block 1075 */ 1076 #define AR933X_SRIF_DDR_DPLL1_REG 0x240 1077 #define AR933X_SRIF_DDR_DPLL2_REG 0x244 1078 #define AR933X_SRIF_DDR_DPLL3_REG 0x248 1079 #define AR933X_SRIF_DDR_DPLL4_REG 0x24c 1080 1081 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 1082 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 1083 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 1084 1085 #define AR934X_SRIF_DDR_DPLL1_REG 0x240 1086 #define AR934X_SRIF_DDR_DPLL2_REG 0x244 1087 #define AR934X_SRIF_DDR_DPLL3_REG 0x248 1088 1089 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 1090 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f 1091 #define AR934X_SRIF_DPLL1_NINT_SHIFT 18 1092 #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff 1093 #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1094 1095 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1096 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 1097 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 1098 1099 #define QCA953X_SRIF_BB_DPLL1_REG 0x180 1100 #define QCA953X_SRIF_BB_DPLL2_REG 0x184 1101 #define QCA953X_SRIF_BB_DPLL3_REG 0x188 1102 1103 #define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 1104 #define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 1105 #define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 1106 1107 #define QCA953X_SRIF_DDR_DPLL1_REG 0x240 1108 #define QCA953X_SRIF_DDR_DPLL2_REG 0x244 1109 #define QCA953X_SRIF_DDR_DPLL3_REG 0x248 1110 1111 #define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 1112 #define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 1113 #define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 1114 1115 #define QCA953X_SRIF_PMU1_REG 0xc40 1116 #define QCA953X_SRIF_PMU2_REG 0xc44 1117 1118 #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 1119 #define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f 1120 1121 #define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 1122 #define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff 1123 #define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1124 1125 #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1126 1127 #define QCA953X_SRIF_DPLL2_KI_SHIFT 29 1128 #define QCA953X_SRIF_DPLL2_KI_MASK 0x3 1129 1130 #define QCA953X_SRIF_DPLL2_KD_SHIFT 25 1131 #define QCA953X_SRIF_DPLL2_KD_MASK 0xf 1132 1133 #define QCA953X_SRIF_DPLL2_PWD BIT(22) 1134 1135 #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 1136 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 1137 1138 /* 1139 * MII_CTRL block 1140 */ 1141 #define AR71XX_MII_REG_MII0_CTRL 0x00 1142 #define AR71XX_MII_REG_MII1_CTRL 0x04 1143 1144 #define AR71XX_MII_CTRL_IF_MASK 3 1145 #define AR71XX_MII_CTRL_SPEED_SHIFT 4 1146 #define AR71XX_MII_CTRL_SPEED_MASK 3 1147 #define AR71XX_MII_CTRL_SPEED_10 0 1148 #define AR71XX_MII_CTRL_SPEED_100 1 1149 #define AR71XX_MII_CTRL_SPEED_1000 2 1150 1151 #define AR71XX_MII0_CTRL_IF_GMII 0 1152 #define AR71XX_MII0_CTRL_IF_MII 1 1153 #define AR71XX_MII0_CTRL_IF_RGMII 2 1154 #define AR71XX_MII0_CTRL_IF_RMII 3 1155 1156 #define AR71XX_MII1_CTRL_IF_RGMII 0 1157 #define AR71XX_MII1_CTRL_IF_RMII 1 1158 1159 /* 1160 * AR933X GMAC interface 1161 */ 1162 #define AR933X_GMAC_REG_ETH_CFG 0x00 1163 1164 #define AR933X_ETH_CFG_RGMII_GE0 BIT(0) 1165 #define AR933X_ETH_CFG_MII_GE0 BIT(1) 1166 #define AR933X_ETH_CFG_GMII_GE0 BIT(2) 1167 #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) 1168 #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) 1169 #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) 1170 #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) 1171 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 1172 #define AR933X_ETH_CFG_RMII_GE0 BIT(9) 1173 #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 1174 #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) 1175 1176 /* 1177 * AR934X GMAC Interface 1178 */ 1179 #define AR934X_GMAC_REG_ETH_CFG 0x00 1180 1181 #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) 1182 #define AR934X_ETH_CFG_MII_GMAC0 BIT(1) 1183 #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) 1184 #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) 1185 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) 1186 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) 1187 #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) 1188 #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) 1189 #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) 1190 #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) 1191 #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) 1192 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) 1193 #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1194 #define AR934X_ETH_CFG_RXD_DELAY BIT(14) 1195 #define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 1196 #define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 1197 #define AR934X_ETH_CFG_RDV_DELAY BIT(16) 1198 #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 1199 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 1200 1201 /* 1202 * QCA953X GMAC Interface 1203 */ 1204 #define QCA953X_GMAC_REG_ETH_CFG 0x00 1205 1206 #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) 1207 #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) 1208 #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) 1209 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1210 1211 /* 1212 * QCA955X GMAC Interface 1213 */ 1214 1215 #define QCA955X_GMAC_REG_ETH_CFG 0x00 1216 1217 #define QCA955X_ETH_CFG_RGMII_EN BIT(0) 1218 #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 1219 1220 #endif /* __ASM_AR71XX_H */ 1221