11d3d0f1fSWills Wang /* 21d3d0f1fSWills Wang * Atheros AR71XX/AR724X/AR913X SoC register definitions 31d3d0f1fSWills Wang * 41d3d0f1fSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 51d3d0f1fSWills Wang * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 61d3d0f1fSWills Wang * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 71d3d0f1fSWills Wang * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 81d3d0f1fSWills Wang * 91d3d0f1fSWills Wang * SPDX-License-Identifier: GPL-2.0+ 101d3d0f1fSWills Wang */ 111d3d0f1fSWills Wang 121d3d0f1fSWills Wang #ifndef __ASM_MACH_AR71XX_REGS_H 131d3d0f1fSWills Wang #define __ASM_MACH_AR71XX_REGS_H 141d3d0f1fSWills Wang 151d3d0f1fSWills Wang #ifndef __ASSEMBLY__ 161d3d0f1fSWills Wang #include <linux/bitops.h> 171d3d0f1fSWills Wang #else 181d3d0f1fSWills Wang #ifndef BIT 191d3d0f1fSWills Wang #define BIT(nr) (1 << (nr)) 201d3d0f1fSWills Wang #endif 211d3d0f1fSWills Wang #endif 221d3d0f1fSWills Wang 231d3d0f1fSWills Wang #define AR71XX_APB_BASE 0x18000000 241d3d0f1fSWills Wang #define AR71XX_GE0_BASE 0x19000000 251d3d0f1fSWills Wang #define AR71XX_GE0_SIZE 0x10000 261d3d0f1fSWills Wang #define AR71XX_GE1_BASE 0x1a000000 271d3d0f1fSWills Wang #define AR71XX_GE1_SIZE 0x10000 281d3d0f1fSWills Wang #define AR71XX_EHCI_BASE 0x1b000000 291d3d0f1fSWills Wang #define AR71XX_EHCI_SIZE 0x1000 301d3d0f1fSWills Wang #define AR71XX_OHCI_BASE 0x1c000000 311d3d0f1fSWills Wang #define AR71XX_OHCI_SIZE 0x1000 321d3d0f1fSWills Wang #define AR71XX_SPI_BASE 0x1f000000 331d3d0f1fSWills Wang #define AR71XX_SPI_SIZE 0x01000000 341d3d0f1fSWills Wang 350a6767efSMarek Vasut #define AR71XX_DDR_CTRL_BASE \ 360a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00000000) 371d3d0f1fSWills Wang #define AR71XX_DDR_CTRL_SIZE 0x100 380a6767efSMarek Vasut #define AR71XX_UART_BASE \ 390a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00020000) 401d3d0f1fSWills Wang #define AR71XX_UART_SIZE 0x100 410a6767efSMarek Vasut #define AR71XX_USB_CTRL_BASE \ 420a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00030000) 431d3d0f1fSWills Wang #define AR71XX_USB_CTRL_SIZE 0x100 440a6767efSMarek Vasut #define AR71XX_GPIO_BASE \ 450a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00040000) 461d3d0f1fSWills Wang #define AR71XX_GPIO_SIZE 0x100 470a6767efSMarek Vasut #define AR71XX_PLL_BASE \ 480a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00050000) 491d3d0f1fSWills Wang #define AR71XX_PLL_SIZE 0x100 500a6767efSMarek Vasut #define AR71XX_RESET_BASE \ 510a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00060000) 521d3d0f1fSWills Wang #define AR71XX_RESET_SIZE 0x100 530a6767efSMarek Vasut #define AR71XX_MII_BASE \ 540a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00070000) 551d3d0f1fSWills Wang #define AR71XX_MII_SIZE 0x100 561d3d0f1fSWills Wang 571d3d0f1fSWills Wang #define AR71XX_PCI_MEM_BASE 0x10000000 581d3d0f1fSWills Wang #define AR71XX_PCI_MEM_SIZE 0x07000000 591d3d0f1fSWills Wang 601d3d0f1fSWills Wang #define AR71XX_PCI_WIN0_OFFS 0x10000000 611d3d0f1fSWills Wang #define AR71XX_PCI_WIN1_OFFS 0x11000000 621d3d0f1fSWills Wang #define AR71XX_PCI_WIN2_OFFS 0x12000000 631d3d0f1fSWills Wang #define AR71XX_PCI_WIN3_OFFS 0x13000000 641d3d0f1fSWills Wang #define AR71XX_PCI_WIN4_OFFS 0x14000000 651d3d0f1fSWills Wang #define AR71XX_PCI_WIN5_OFFS 0x15000000 661d3d0f1fSWills Wang #define AR71XX_PCI_WIN6_OFFS 0x16000000 671d3d0f1fSWills Wang #define AR71XX_PCI_WIN7_OFFS 0x07000000 681d3d0f1fSWills Wang 691d3d0f1fSWills Wang #define AR71XX_PCI_CFG_BASE \ 701d3d0f1fSWills Wang (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) 711d3d0f1fSWills Wang #define AR71XX_PCI_CFG_SIZE 0x100 721d3d0f1fSWills Wang 730a6767efSMarek Vasut #define AR7240_USB_CTRL_BASE \ 740a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00030000) 751d3d0f1fSWills Wang #define AR7240_USB_CTRL_SIZE 0x100 761d3d0f1fSWills Wang #define AR7240_OHCI_BASE 0x1b000000 771d3d0f1fSWills Wang #define AR7240_OHCI_SIZE 0x1000 781d3d0f1fSWills Wang 791d3d0f1fSWills Wang #define AR724X_PCI_MEM_BASE 0x10000000 801d3d0f1fSWills Wang #define AR724X_PCI_MEM_SIZE 0x04000000 811d3d0f1fSWills Wang 821d3d0f1fSWills Wang #define AR724X_PCI_CFG_BASE 0x14000000 831d3d0f1fSWills Wang #define AR724X_PCI_CFG_SIZE 0x1000 840a6767efSMarek Vasut #define AR724X_PCI_CRP_BASE \ 850a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000c0000) 861d3d0f1fSWills Wang #define AR724X_PCI_CRP_SIZE 0x1000 870a6767efSMarek Vasut #define AR724X_PCI_CTRL_BASE \ 880a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000f0000) 891d3d0f1fSWills Wang #define AR724X_PCI_CTRL_SIZE 0x100 901d3d0f1fSWills Wang 911d3d0f1fSWills Wang #define AR724X_EHCI_BASE 0x1b000000 921d3d0f1fSWills Wang #define AR724X_EHCI_SIZE 0x1000 931d3d0f1fSWills Wang 941d3d0f1fSWills Wang #define AR913X_EHCI_BASE 0x1b000000 951d3d0f1fSWills Wang #define AR913X_EHCI_SIZE 0x1000 960a6767efSMarek Vasut #define AR913X_WMAC_BASE \ 970a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000C0000) 981d3d0f1fSWills Wang #define AR913X_WMAC_SIZE 0x30000 991d3d0f1fSWills Wang 1000a6767efSMarek Vasut #define AR933X_UART_BASE \ 1010a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00020000) 1021d3d0f1fSWills Wang #define AR933X_UART_SIZE 0x14 1030a6767efSMarek Vasut #define AR933X_GMAC_BASE \ 1040a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00070000) 1051d3d0f1fSWills Wang #define AR933X_GMAC_SIZE 0x04 1060a6767efSMarek Vasut #define AR933X_WMAC_BASE \ 1070a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00100000) 1081d3d0f1fSWills Wang #define AR933X_WMAC_SIZE 0x20000 1090a6767efSMarek Vasut #define AR933X_RTC_BASE \ 1100a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00107000) 1111d3d0f1fSWills Wang #define AR933X_RTC_SIZE 0x1000 1121d3d0f1fSWills Wang #define AR933X_EHCI_BASE 0x1b000000 1131d3d0f1fSWills Wang #define AR933X_EHCI_SIZE 0x1000 1140a6767efSMarek Vasut #define AR933X_SRIF_BASE \ 1150a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00116000) 1161d3d0f1fSWills Wang #define AR933X_SRIF_SIZE 0x1000 1171d3d0f1fSWills Wang 1180a6767efSMarek Vasut #define AR934X_GMAC_BASE \ 1190a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00070000) 1201d3d0f1fSWills Wang #define AR934X_GMAC_SIZE 0x14 1210a6767efSMarek Vasut #define AR934X_WMAC_BASE \ 1220a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00100000) 1231d3d0f1fSWills Wang #define AR934X_WMAC_SIZE 0x20000 1241d3d0f1fSWills Wang #define AR934X_EHCI_BASE 0x1b000000 1251d3d0f1fSWills Wang #define AR934X_EHCI_SIZE 0x200 1261d3d0f1fSWills Wang #define AR934X_NFC_BASE 0x1b000200 1271d3d0f1fSWills Wang #define AR934X_NFC_SIZE 0xb8 1280a6767efSMarek Vasut #define AR934X_SRIF_BASE \ 1290a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00116000) 1301d3d0f1fSWills Wang #define AR934X_SRIF_SIZE 0x1000 1311d3d0f1fSWills Wang 1320a6767efSMarek Vasut #define QCA953X_GMAC_BASE \ 1330a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00070000) 1341d3d0f1fSWills Wang #define QCA953X_GMAC_SIZE 0x14 1350a6767efSMarek Vasut #define QCA953X_WMAC_BASE \ 1360a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00100000) 1371d3d0f1fSWills Wang #define QCA953X_WMAC_SIZE 0x20000 1380a6767efSMarek Vasut #define QCA953X_RTC_BASE \ 1390a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00107000) 1401d3d0f1fSWills Wang #define QCA953X_RTC_SIZE 0x1000 1411d3d0f1fSWills Wang #define QCA953X_EHCI_BASE 0x1b000000 1421d3d0f1fSWills Wang #define QCA953X_EHCI_SIZE 0x200 1430a6767efSMarek Vasut #define QCA953X_SRIF_BASE \ 1440a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00116000) 1451d3d0f1fSWills Wang #define QCA953X_SRIF_SIZE 0x1000 1461d3d0f1fSWills Wang 1471d3d0f1fSWills Wang #define QCA953X_PCI_CFG_BASE0 0x14000000 1480a6767efSMarek Vasut #define QCA953X_PCI_CTRL_BASE0 \ 1490a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000f0000) 1500a6767efSMarek Vasut #define QCA953X_PCI_CRP_BASE0 \ 1510a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000c0000) 1521d3d0f1fSWills Wang #define QCA953X_PCI_MEM_BASE0 0x10000000 1531d3d0f1fSWills Wang #define QCA953X_PCI_MEM_SIZE 0x02000000 1541d3d0f1fSWills Wang 1551d3d0f1fSWills Wang #define QCA955X_PCI_MEM_BASE0 0x10000000 1561d3d0f1fSWills Wang #define QCA955X_PCI_MEM_BASE1 0x12000000 1571d3d0f1fSWills Wang #define QCA955X_PCI_MEM_SIZE 0x02000000 1581d3d0f1fSWills Wang #define QCA955X_PCI_CFG_BASE0 0x14000000 1591d3d0f1fSWills Wang #define QCA955X_PCI_CFG_BASE1 0x16000000 1601d3d0f1fSWills Wang #define QCA955X_PCI_CFG_SIZE 0x1000 1610a6767efSMarek Vasut #define QCA955X_PCI_CRP_BASE0 \ 1620a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000c0000) 1630a6767efSMarek Vasut #define QCA955X_PCI_CRP_BASE1 \ 1640a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00250000) 1651d3d0f1fSWills Wang #define QCA955X_PCI_CRP_SIZE 0x1000 1660a6767efSMarek Vasut #define QCA955X_PCI_CTRL_BASE0 \ 1670a6767efSMarek Vasut (AR71XX_APB_BASE + 0x000f0000) 1680a6767efSMarek Vasut #define QCA955X_PCI_CTRL_BASE1 \ 1690a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00280000) 1701d3d0f1fSWills Wang #define QCA955X_PCI_CTRL_SIZE 0x100 1711d3d0f1fSWills Wang 1720a6767efSMarek Vasut #define QCA955X_GMAC_BASE \ 1730a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00070000) 1741d3d0f1fSWills Wang #define QCA955X_GMAC_SIZE 0x40 1750a6767efSMarek Vasut #define QCA955X_WMAC_BASE \ 1760a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00100000) 1771d3d0f1fSWills Wang #define QCA955X_WMAC_SIZE 0x20000 1781d3d0f1fSWills Wang #define QCA955X_EHCI0_BASE 0x1b000000 1791d3d0f1fSWills Wang #define QCA955X_EHCI1_BASE 0x1b400000 1801d3d0f1fSWills Wang #define QCA955X_EHCI_SIZE 0x1000 1811d3d0f1fSWills Wang #define QCA955X_NFC_BASE 0x1b800200 1821d3d0f1fSWills Wang #define QCA955X_NFC_SIZE 0xb8 1831d3d0f1fSWills Wang 1841d3d0f1fSWills Wang #define QCA956X_PCI_MEM_BASE1 0x12000000 1851d3d0f1fSWills Wang #define QCA956X_PCI_MEM_SIZE 0x02000000 1861d3d0f1fSWills Wang #define QCA956X_PCI_CFG_BASE1 0x16000000 1871d3d0f1fSWills Wang #define QCA956X_PCI_CFG_SIZE 0x1000 1880a6767efSMarek Vasut #define QCA956X_PCI_CRP_BASE1 \ 1890a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00250000) 1901d3d0f1fSWills Wang #define QCA956X_PCI_CRP_SIZE 0x1000 1910a6767efSMarek Vasut #define QCA956X_PCI_CTRL_BASE1 \ 1920a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00280000) 1931d3d0f1fSWills Wang #define QCA956X_PCI_CTRL_SIZE 0x100 1941d3d0f1fSWills Wang 1950a6767efSMarek Vasut #define QCA956X_WMAC_BASE \ 1960a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00100000) 1971d3d0f1fSWills Wang #define QCA956X_WMAC_SIZE 0x20000 1981d3d0f1fSWills Wang #define QCA956X_EHCI0_BASE 0x1b000000 1991d3d0f1fSWills Wang #define QCA956X_EHCI1_BASE 0x1b400000 2001d3d0f1fSWills Wang #define QCA956X_EHCI_SIZE 0x200 2010a6767efSMarek Vasut #define QCA956X_GMAC_BASE \ 2020a6767efSMarek Vasut (AR71XX_APB_BASE + 0x00070000) 2031d3d0f1fSWills Wang #define QCA956X_GMAC_SIZE 0x64 2041d3d0f1fSWills Wang 2051d3d0f1fSWills Wang /* 2061d3d0f1fSWills Wang * DDR_CTRL block 2071d3d0f1fSWills Wang */ 2081d3d0f1fSWills Wang #define AR71XX_DDR_REG_CONFIG 0x00 2091d3d0f1fSWills Wang #define AR71XX_DDR_REG_CONFIG2 0x04 2101d3d0f1fSWills Wang #define AR71XX_DDR_REG_MODE 0x08 2111d3d0f1fSWills Wang #define AR71XX_DDR_REG_EMR 0x0c 2121d3d0f1fSWills Wang #define AR71XX_DDR_REG_CONTROL 0x10 2131d3d0f1fSWills Wang #define AR71XX_DDR_REG_REFRESH 0x14 2141d3d0f1fSWills Wang #define AR71XX_DDR_REG_RD_CYCLE 0x18 2151d3d0f1fSWills Wang #define AR71XX_DDR_REG_TAP_CTRL0 0x1c 2161d3d0f1fSWills Wang #define AR71XX_DDR_REG_TAP_CTRL1 0x20 2171d3d0f1fSWills Wang 2181d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN0 0x7c 2191d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN1 0x80 2201d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN2 0x84 2211d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN3 0x88 2221d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN4 0x8c 2231d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN5 0x90 2241d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN6 0x94 2251d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN7 0x98 2261d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_GE0 0x9c 2271d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 2281d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_USB 0xa4 2291d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 2301d3d0f1fSWills Wang 2311d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_GE0 0x7c 2321d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_GE1 0x80 2331d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_USB 0x84 2341d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_PCIE 0x88 2351d3d0f1fSWills Wang 2361d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_GE0 0x7c 2371d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_GE1 0x80 2381d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_USB 0x84 2391d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_WMAC 0x88 2401d3d0f1fSWills Wang 2411d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_GE0 0x7c 2421d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_GE1 0x80 2431d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_USB 0x84 2441d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_WMAC 0x88 2451d3d0f1fSWills Wang #define AR933X_DDR_REG_DDR2_CONFIG 0x8c 2461d3d0f1fSWills Wang #define AR933X_DDR_REG_EMR2 0x90 2471d3d0f1fSWills Wang #define AR933X_DDR_REG_EMR3 0x94 2481d3d0f1fSWills Wang #define AR933X_DDR_REG_BURST 0x98 2491d3d0f1fSWills Wang #define AR933X_DDR_REG_TIMEOUT_MAX 0x9c 2501d3d0f1fSWills Wang #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c 2511d3d0f1fSWills Wang #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c 2521d3d0f1fSWills Wang 253*e08539b7SMarek Vasut #define AR934X_DDR_REG_TAP_CTRL2 0x24 254*e08539b7SMarek Vasut #define AR934X_DDR_REG_TAP_CTRL3 0x28 2551d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_GE0 0x9c 2561d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_GE1 0xa0 2571d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_USB 0xa4 2581d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 2591d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_WMAC 0xac 260*e08539b7SMarek Vasut #define AR934X_DDR_REG_FLUSH_SRC1 0xb0 261*e08539b7SMarek Vasut #define AR934X_DDR_REG_FLUSH_SRC2 0xb4 262*e08539b7SMarek Vasut #define AR934X_DDR_REG_DDR2_CONFIG 0xb8 263*e08539b7SMarek Vasut #define AR934X_DDR_REG_EMR2 0xbc 264*e08539b7SMarek Vasut #define AR934X_DDR_REG_EMR3 0xc0 265*e08539b7SMarek Vasut #define AR934X_DDR_REG_BURST 0xc4 266*e08539b7SMarek Vasut #define AR934X_DDR_REG_BURST2 0xc8 267*e08539b7SMarek Vasut #define AR934X_DDR_REG_TIMEOUT_MAX 0xcc 268*e08539b7SMarek Vasut #define AR934X_DDR_REG_CTL_CONF 0x108 2691d3d0f1fSWills Wang 2701d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_GE0 0x9c 2711d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_GE1 0xa0 2721d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_USB 0xa4 2731d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 2741d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_WMAC 0xac 2751d3d0f1fSWills Wang #define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 2761d3d0f1fSWills Wang #define QCA953X_DDR_REG_BURST 0xc4 2771d3d0f1fSWills Wang #define QCA953X_DDR_REG_BURST2 0xc8 2781d3d0f1fSWills Wang #define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc 2791d3d0f1fSWills Wang #define QCA953X_DDR_REG_CTL_CONF 0x108 2801d3d0f1fSWills Wang #define QCA953X_DDR_REG_CONFIG3 0x15c 2811d3d0f1fSWills Wang 2821d3d0f1fSWills Wang /* 2831d3d0f1fSWills Wang * PLL block 2841d3d0f1fSWills Wang */ 2851d3d0f1fSWills Wang #define AR71XX_PLL_REG_CPU_CONFIG 0x00 2861d3d0f1fSWills Wang #define AR71XX_PLL_REG_SEC_CONFIG 0x04 2871d3d0f1fSWills Wang #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 2881d3d0f1fSWills Wang #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 2891d3d0f1fSWills Wang 2901d3d0f1fSWills Wang #define AR71XX_PLL_DIV_SHIFT 3 2911d3d0f1fSWills Wang #define AR71XX_PLL_DIV_MASK 0x1f 2921d3d0f1fSWills Wang #define AR71XX_CPU_DIV_SHIFT 16 2931d3d0f1fSWills Wang #define AR71XX_CPU_DIV_MASK 0x3 2941d3d0f1fSWills Wang #define AR71XX_DDR_DIV_SHIFT 18 2951d3d0f1fSWills Wang #define AR71XX_DDR_DIV_MASK 0x3 2961d3d0f1fSWills Wang #define AR71XX_AHB_DIV_SHIFT 20 2971d3d0f1fSWills Wang #define AR71XX_AHB_DIV_MASK 0x7 2981d3d0f1fSWills Wang 2991d3d0f1fSWills Wang #define AR71XX_ETH0_PLL_SHIFT 17 3001d3d0f1fSWills Wang #define AR71XX_ETH1_PLL_SHIFT 19 3011d3d0f1fSWills Wang 3021d3d0f1fSWills Wang #define AR724X_PLL_REG_CPU_CONFIG 0x00 3031d3d0f1fSWills Wang #define AR724X_PLL_REG_PCIE_CONFIG 0x18 3041d3d0f1fSWills Wang 3051d3d0f1fSWills Wang #define AR724X_PLL_DIV_SHIFT 0 3061d3d0f1fSWills Wang #define AR724X_PLL_DIV_MASK 0x3ff 3071d3d0f1fSWills Wang #define AR724X_PLL_REF_DIV_SHIFT 10 3081d3d0f1fSWills Wang #define AR724X_PLL_REF_DIV_MASK 0xf 3091d3d0f1fSWills Wang #define AR724X_AHB_DIV_SHIFT 19 3101d3d0f1fSWills Wang #define AR724X_AHB_DIV_MASK 0x1 3111d3d0f1fSWills Wang #define AR724X_DDR_DIV_SHIFT 22 3121d3d0f1fSWills Wang #define AR724X_DDR_DIV_MASK 0x3 3131d3d0f1fSWills Wang 3141d3d0f1fSWills Wang #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c 3151d3d0f1fSWills Wang 3161d3d0f1fSWills Wang #define AR913X_PLL_REG_CPU_CONFIG 0x00 3171d3d0f1fSWills Wang #define AR913X_PLL_REG_ETH_CONFIG 0x04 3181d3d0f1fSWills Wang #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 3191d3d0f1fSWills Wang #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 3201d3d0f1fSWills Wang 3211d3d0f1fSWills Wang #define AR913X_PLL_DIV_SHIFT 0 3221d3d0f1fSWills Wang #define AR913X_PLL_DIV_MASK 0x3ff 3231d3d0f1fSWills Wang #define AR913X_DDR_DIV_SHIFT 22 3241d3d0f1fSWills Wang #define AR913X_DDR_DIV_MASK 0x3 3251d3d0f1fSWills Wang #define AR913X_AHB_DIV_SHIFT 19 3261d3d0f1fSWills Wang #define AR913X_AHB_DIV_MASK 0x1 3271d3d0f1fSWills Wang 3281d3d0f1fSWills Wang #define AR913X_ETH0_PLL_SHIFT 20 3291d3d0f1fSWills Wang #define AR913X_ETH1_PLL_SHIFT 22 3301d3d0f1fSWills Wang 3311d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_REG 0x00 3321d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_REG 0x08 3331d3d0f1fSWills Wang #define AR933X_PLL_DITHER_FRAC_REG 0x10 3341d3d0f1fSWills Wang 3351d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 3361d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 3371d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 3381d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 3391d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 3401d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 3411d3d0f1fSWills Wang 3421d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) 3431d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 3441d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 3451d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 3461d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 3471d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 3481d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 3491d3d0f1fSWills Wang 3501d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_REG 0x00 3511d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_REG 0x04 3521d3d0f1fSWills Wang #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 3531d3d0f1fSWills Wang #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 3541d3d0f1fSWills Wang #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c 355*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_REG 0x44 356*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_REG 0x48 3571d3d0f1fSWills Wang 3581d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 3591d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 3601d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 3611d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 3621d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 3631d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 364*e08539b7SMarek Vasut #define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17 365*e08539b7SMarek Vasut #define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3 3661d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 3671d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 368*e08539b7SMarek Vasut #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30) 369*e08539b7SMarek Vasut #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31) 3701d3d0f1fSWills Wang 3711d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 3721d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 3731d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 3741d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 3751d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 3761d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 377*e08539b7SMarek Vasut #define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21 378*e08539b7SMarek Vasut #define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3 3791d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 3801d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 381*e08539b7SMarek Vasut #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30) 382*e08539b7SMarek Vasut #define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31) 3831d3d0f1fSWills Wang 3841d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 3851d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 3861d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 3871d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 3881d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 3891d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 3901d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 3911d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 3921d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 3931d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 3941d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 3951d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 3961d3d0f1fSWills Wang 3971d3d0f1fSWills Wang #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) 3981d3d0f1fSWills Wang 399*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 400*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 401*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10 402*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 403*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 404*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 405*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 406*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 407*e08539b7SMarek Vasut #define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31) 408*e08539b7SMarek Vasut 409*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 410*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 411*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 412*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 413*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 414*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 415*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 416*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 417*e08539b7SMarek Vasut #define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31) 418*e08539b7SMarek Vasut 4191d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_REG 0x00 4201d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_REG 0x04 4211d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_REG 0x08 4221d3d0f1fSWills Wang #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 4231d3d0f1fSWills Wang #define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c 4241d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 4251d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 4261d3d0f1fSWills Wang 4271d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 4281d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 4291d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 4301d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f 4311d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 4321d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 4331d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 4341d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 4351d3d0f1fSWills Wang 4361d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 4371d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 4381d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 4391d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f 4401d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 4411d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 4421d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 4431d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 4441d3d0f1fSWills Wang 4451d3d0f1fSWills Wang #define QCA953X_PLL_CONFIG_PWD BIT(30) 4461d3d0f1fSWills Wang 4471d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 4481d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 4491d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 4501d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 4511d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 4521d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 4531d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 4541d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 4551d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 4561d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 4571d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 4581d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 4591d3d0f1fSWills Wang 4601d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 4611d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 4621d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 4631d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 4641d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 4651d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 4661d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 4671d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 4681d3d0f1fSWills Wang 4691d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 4701d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 4711d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 4721d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 4731d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 4741d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 4751d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 4761d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 4771d3d0f1fSWills Wang 4781d3d0f1fSWills Wang #define QCA953X_PLL_DIT_FRAC_EN BIT(31) 4791d3d0f1fSWills Wang 4801d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_REG 0x00 4811d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_REG 0x04 4821d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_REG 0x08 4831d3d0f1fSWills Wang #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 4841d3d0f1fSWills Wang #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 4851d3d0f1fSWills Wang 4861d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 4871d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 4881d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 4891d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 4901d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 4911d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 4921d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 4931d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 4941d3d0f1fSWills Wang 4951d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 4961d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 4971d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 4981d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 4991d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 5001d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 5011d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 5021d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 5031d3d0f1fSWills Wang 5041d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 5051d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 5061d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 5071d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 5081d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 5091d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 5101d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 5111d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 5121d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 5131d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 5141d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 5151d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 5161d3d0f1fSWills Wang 5171d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_REG 0x00 5181d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 5191d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_REG 0x08 5201d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c 5211d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_REG 0x10 5221d3d0f1fSWills Wang 5231d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 5241d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 5251d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 5261d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 5271d3d0f1fSWills Wang 5281d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 5291d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f 5301d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 5311d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff 5321d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 5331d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff 5341d3d0f1fSWills Wang 5351d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 5361d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 5371d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 5381d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 5391d3d0f1fSWills Wang 5401d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 5411d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f 5421d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 5431d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff 5441d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 5451d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff 5461d3d0f1fSWills Wang 5471d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 5481d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 5491d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 5501d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 5511d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 5521d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 5531d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 5541d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 5551d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 5561d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) 5571d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) 5581d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 5591d3d0f1fSWills Wang 5601d3d0f1fSWills Wang /* 5611d3d0f1fSWills Wang * USB_CONFIG block 5621d3d0f1fSWills Wang */ 5631d3d0f1fSWills Wang #define AR71XX_USB_CTRL_REG_FLADJ 0x00 5641d3d0f1fSWills Wang #define AR71XX_USB_CTRL_REG_CONFIG 0x04 5651d3d0f1fSWills Wang 5661d3d0f1fSWills Wang /* 5671d3d0f1fSWills Wang * RESET block 5681d3d0f1fSWills Wang */ 5691d3d0f1fSWills Wang #define AR71XX_RESET_REG_TIMER 0x00 5701d3d0f1fSWills Wang #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 5711d3d0f1fSWills Wang #define AR71XX_RESET_REG_WDOG_CTRL 0x08 5721d3d0f1fSWills Wang #define AR71XX_RESET_REG_WDOG 0x0c 5731d3d0f1fSWills Wang #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 5741d3d0f1fSWills Wang #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 5751d3d0f1fSWills Wang #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 5761d3d0f1fSWills Wang #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 5771d3d0f1fSWills Wang #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 5781d3d0f1fSWills Wang #define AR71XX_RESET_REG_RESET_MODULE 0x24 5791d3d0f1fSWills Wang #define AR71XX_RESET_REG_PERFC_CTRL 0x2c 5801d3d0f1fSWills Wang #define AR71XX_RESET_REG_PERFC0 0x30 5811d3d0f1fSWills Wang #define AR71XX_RESET_REG_PERFC1 0x34 5821d3d0f1fSWills Wang #define AR71XX_RESET_REG_REV_ID 0x90 5831d3d0f1fSWills Wang 5841d3d0f1fSWills Wang #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 5851d3d0f1fSWills Wang #define AR913X_RESET_REG_RESET_MODULE 0x1c 5861d3d0f1fSWills Wang #define AR913X_RESET_REG_PERF_CTRL 0x20 5871d3d0f1fSWills Wang #define AR913X_RESET_REG_PERFC0 0x24 5881d3d0f1fSWills Wang #define AR913X_RESET_REG_PERFC1 0x28 5891d3d0f1fSWills Wang 5901d3d0f1fSWills Wang #define AR724X_RESET_REG_RESET_MODULE 0x1c 5911d3d0f1fSWills Wang 5921d3d0f1fSWills Wang #define AR933X_RESET_REG_RESET_MODULE 0x1c 5931d3d0f1fSWills Wang #define AR933X_RESET_REG_BOOTSTRAP 0xac 5941d3d0f1fSWills Wang 5951d3d0f1fSWills Wang #define AR934X_RESET_REG_RESET_MODULE 0x1c 5961d3d0f1fSWills Wang #define AR934X_RESET_REG_BOOTSTRAP 0xb0 5971d3d0f1fSWills Wang #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 5981d3d0f1fSWills Wang 5991d3d0f1fSWills Wang #define QCA953X_RESET_REG_RESET_MODULE 0x1c 6001d3d0f1fSWills Wang #define QCA953X_RESET_REG_BOOTSTRAP 0xb0 6011d3d0f1fSWills Wang #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 6021d3d0f1fSWills Wang 6031d3d0f1fSWills Wang #define QCA955X_RESET_REG_RESET_MODULE 0x1c 6041d3d0f1fSWills Wang #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 6051d3d0f1fSWills Wang #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac 6061d3d0f1fSWills Wang 6071d3d0f1fSWills Wang #define QCA956X_RESET_REG_RESET_MODULE 0x1c 6081d3d0f1fSWills Wang #define QCA956X_RESET_REG_BOOTSTRAP 0xb0 6091d3d0f1fSWills Wang #define QCA956X_RESET_REG_EXT_INT_STATUS 0xac 6101d3d0f1fSWills Wang 6111d3d0f1fSWills Wang #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) 6121d3d0f1fSWills Wang #define MISC_INT_ETHSW BIT(12) 6131d3d0f1fSWills Wang #define MISC_INT_TIMER4 BIT(10) 6141d3d0f1fSWills Wang #define MISC_INT_TIMER3 BIT(9) 6151d3d0f1fSWills Wang #define MISC_INT_TIMER2 BIT(8) 6161d3d0f1fSWills Wang #define MISC_INT_DMA BIT(7) 6171d3d0f1fSWills Wang #define MISC_INT_OHCI BIT(6) 6181d3d0f1fSWills Wang #define MISC_INT_PERFC BIT(5) 6191d3d0f1fSWills Wang #define MISC_INT_WDOG BIT(4) 6201d3d0f1fSWills Wang #define MISC_INT_UART BIT(3) 6211d3d0f1fSWills Wang #define MISC_INT_GPIO BIT(2) 6221d3d0f1fSWills Wang #define MISC_INT_ERROR BIT(1) 6231d3d0f1fSWills Wang #define MISC_INT_TIMER BIT(0) 6241d3d0f1fSWills Wang 6251d3d0f1fSWills Wang #define AR71XX_RESET_EXTERNAL BIT(28) 6261d3d0f1fSWills Wang #define AR71XX_RESET_FULL_CHIP BIT(24) 6271d3d0f1fSWills Wang #define AR71XX_RESET_CPU_NMI BIT(21) 6281d3d0f1fSWills Wang #define AR71XX_RESET_CPU_COLD BIT(20) 6291d3d0f1fSWills Wang #define AR71XX_RESET_DMA BIT(19) 6301d3d0f1fSWills Wang #define AR71XX_RESET_SLIC BIT(18) 6311d3d0f1fSWills Wang #define AR71XX_RESET_STEREO BIT(17) 6321d3d0f1fSWills Wang #define AR71XX_RESET_DDR BIT(16) 6331d3d0f1fSWills Wang #define AR71XX_RESET_GE1_MAC BIT(13) 6341d3d0f1fSWills Wang #define AR71XX_RESET_GE1_PHY BIT(12) 6351d3d0f1fSWills Wang #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 6361d3d0f1fSWills Wang #define AR71XX_RESET_GE0_MAC BIT(9) 6371d3d0f1fSWills Wang #define AR71XX_RESET_GE0_PHY BIT(8) 6381d3d0f1fSWills Wang #define AR71XX_RESET_USB_OHCI_DLL BIT(6) 6391d3d0f1fSWills Wang #define AR71XX_RESET_USB_HOST BIT(5) 6401d3d0f1fSWills Wang #define AR71XX_RESET_USB_PHY BIT(4) 6411d3d0f1fSWills Wang #define AR71XX_RESET_PCI_BUS BIT(1) 6421d3d0f1fSWills Wang #define AR71XX_RESET_PCI_CORE BIT(0) 6431d3d0f1fSWills Wang 6441d3d0f1fSWills Wang #define AR7240_RESET_USB_HOST BIT(5) 6451d3d0f1fSWills Wang #define AR7240_RESET_OHCI_DLL BIT(3) 6461d3d0f1fSWills Wang 6471d3d0f1fSWills Wang #define AR724X_RESET_GE1_MDIO BIT(23) 6481d3d0f1fSWills Wang #define AR724X_RESET_GE0_MDIO BIT(22) 6491d3d0f1fSWills Wang #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 6501d3d0f1fSWills Wang #define AR724X_RESET_PCIE_PHY BIT(7) 6511d3d0f1fSWills Wang #define AR724X_RESET_PCIE BIT(6) 6521d3d0f1fSWills Wang #define AR724X_RESET_USB_HOST BIT(5) 6531d3d0f1fSWills Wang #define AR724X_RESET_USB_PHY BIT(4) 6541d3d0f1fSWills Wang #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 6551d3d0f1fSWills Wang 6561d3d0f1fSWills Wang #define AR913X_RESET_AMBA2WMAC BIT(22) 6571d3d0f1fSWills Wang #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 6581d3d0f1fSWills Wang #define AR913X_RESET_USB_HOST BIT(5) 6591d3d0f1fSWills Wang #define AR913X_RESET_USB_PHY BIT(4) 6601d3d0f1fSWills Wang 6611d3d0f1fSWills Wang #define AR933X_RESET_GE1_MDIO BIT(23) 6621d3d0f1fSWills Wang #define AR933X_RESET_GE0_MDIO BIT(22) 6631d3d0f1fSWills Wang #define AR933X_RESET_GE1_MAC BIT(13) 6641d3d0f1fSWills Wang #define AR933X_RESET_WMAC BIT(11) 6651d3d0f1fSWills Wang #define AR933X_RESET_GE0_MAC BIT(9) 6664771bbeeSMarek Vasut #define AR933X_RESET_ETH_SWITCH BIT(8) 6671d3d0f1fSWills Wang #define AR933X_RESET_USB_HOST BIT(5) 6681d3d0f1fSWills Wang #define AR933X_RESET_USB_PHY BIT(4) 6691d3d0f1fSWills Wang #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 6701d3d0f1fSWills Wang 6711d3d0f1fSWills Wang #define AR934X_RESET_HOST BIT(31) 6721d3d0f1fSWills Wang #define AR934X_RESET_SLIC BIT(30) 6731d3d0f1fSWills Wang #define AR934X_RESET_HDMA BIT(29) 6741d3d0f1fSWills Wang #define AR934X_RESET_EXTERNAL BIT(28) 6751d3d0f1fSWills Wang #define AR934X_RESET_RTC BIT(27) 6761d3d0f1fSWills Wang #define AR934X_RESET_PCIE_EP_INT BIT(26) 6771d3d0f1fSWills Wang #define AR934X_RESET_CHKSUM_ACC BIT(25) 6781d3d0f1fSWills Wang #define AR934X_RESET_FULL_CHIP BIT(24) 6791d3d0f1fSWills Wang #define AR934X_RESET_GE1_MDIO BIT(23) 6801d3d0f1fSWills Wang #define AR934X_RESET_GE0_MDIO BIT(22) 6811d3d0f1fSWills Wang #define AR934X_RESET_CPU_NMI BIT(21) 6821d3d0f1fSWills Wang #define AR934X_RESET_CPU_COLD BIT(20) 6831d3d0f1fSWills Wang #define AR934X_RESET_HOST_RESET_INT BIT(19) 6841d3d0f1fSWills Wang #define AR934X_RESET_PCIE_EP BIT(18) 6851d3d0f1fSWills Wang #define AR934X_RESET_UART1 BIT(17) 6861d3d0f1fSWills Wang #define AR934X_RESET_DDR BIT(16) 6871d3d0f1fSWills Wang #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 6881d3d0f1fSWills Wang #define AR934X_RESET_NANDF BIT(14) 6891d3d0f1fSWills Wang #define AR934X_RESET_GE1_MAC BIT(13) 6901d3d0f1fSWills Wang #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) 6911d3d0f1fSWills Wang #define AR934X_RESET_USB_PHY_ANALOG BIT(11) 6921d3d0f1fSWills Wang #define AR934X_RESET_HOST_DMA_INT BIT(10) 6931d3d0f1fSWills Wang #define AR934X_RESET_GE0_MAC BIT(9) 6941d3d0f1fSWills Wang #define AR934X_RESET_ETH_SWITCH BIT(8) 6951d3d0f1fSWills Wang #define AR934X_RESET_PCIE_PHY BIT(7) 6961d3d0f1fSWills Wang #define AR934X_RESET_PCIE BIT(6) 6971d3d0f1fSWills Wang #define AR934X_RESET_USB_HOST BIT(5) 6981d3d0f1fSWills Wang #define AR934X_RESET_USB_PHY BIT(4) 6991d3d0f1fSWills Wang #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 7001d3d0f1fSWills Wang #define AR934X_RESET_LUT BIT(2) 7011d3d0f1fSWills Wang #define AR934X_RESET_MBOX BIT(1) 7021d3d0f1fSWills Wang #define AR934X_RESET_I2S BIT(0) 7031d3d0f1fSWills Wang 7041d3d0f1fSWills Wang #define QCA953X_RESET_USB_EXT_PWR BIT(29) 7051d3d0f1fSWills Wang #define QCA953X_RESET_EXTERNAL BIT(28) 7061d3d0f1fSWills Wang #define QCA953X_RESET_RTC BIT(27) 7071d3d0f1fSWills Wang #define QCA953X_RESET_FULL_CHIP BIT(24) 7081d3d0f1fSWills Wang #define QCA953X_RESET_GE1_MDIO BIT(23) 7091d3d0f1fSWills Wang #define QCA953X_RESET_GE0_MDIO BIT(22) 7101d3d0f1fSWills Wang #define QCA953X_RESET_CPU_NMI BIT(21) 7111d3d0f1fSWills Wang #define QCA953X_RESET_CPU_COLD BIT(20) 7121d3d0f1fSWills Wang #define QCA953X_RESET_DDR BIT(16) 7131d3d0f1fSWills Wang #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 7141d3d0f1fSWills Wang #define QCA953X_RESET_GE1_MAC BIT(13) 7151d3d0f1fSWills Wang #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) 7161d3d0f1fSWills Wang #define QCA953X_RESET_USB_PHY_ANALOG BIT(11) 7171d3d0f1fSWills Wang #define QCA953X_RESET_GE0_MAC BIT(9) 7181d3d0f1fSWills Wang #define QCA953X_RESET_ETH_SWITCH BIT(8) 7191d3d0f1fSWills Wang #define QCA953X_RESET_PCIE_PHY BIT(7) 7201d3d0f1fSWills Wang #define QCA953X_RESET_PCIE BIT(6) 7211d3d0f1fSWills Wang #define QCA953X_RESET_USB_HOST BIT(5) 7221d3d0f1fSWills Wang #define QCA953X_RESET_USB_PHY BIT(4) 7231d3d0f1fSWills Wang #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) 7241d3d0f1fSWills Wang 7251d3d0f1fSWills Wang #define QCA955X_RESET_HOST BIT(31) 7261d3d0f1fSWills Wang #define QCA955X_RESET_SLIC BIT(30) 7271d3d0f1fSWills Wang #define QCA955X_RESET_HDMA BIT(29) 7281d3d0f1fSWills Wang #define QCA955X_RESET_EXTERNAL BIT(28) 7291d3d0f1fSWills Wang #define QCA955X_RESET_RTC BIT(27) 7301d3d0f1fSWills Wang #define QCA955X_RESET_PCIE_EP_INT BIT(26) 7311d3d0f1fSWills Wang #define QCA955X_RESET_CHKSUM_ACC BIT(25) 7321d3d0f1fSWills Wang #define QCA955X_RESET_FULL_CHIP BIT(24) 7331d3d0f1fSWills Wang #define QCA955X_RESET_GE1_MDIO BIT(23) 7341d3d0f1fSWills Wang #define QCA955X_RESET_GE0_MDIO BIT(22) 7351d3d0f1fSWills Wang #define QCA955X_RESET_CPU_NMI BIT(21) 7361d3d0f1fSWills Wang #define QCA955X_RESET_CPU_COLD BIT(20) 7371d3d0f1fSWills Wang #define QCA955X_RESET_HOST_RESET_INT BIT(19) 7381d3d0f1fSWills Wang #define QCA955X_RESET_PCIE_EP BIT(18) 7391d3d0f1fSWills Wang #define QCA955X_RESET_UART1 BIT(17) 7401d3d0f1fSWills Wang #define QCA955X_RESET_DDR BIT(16) 7411d3d0f1fSWills Wang #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 7421d3d0f1fSWills Wang #define QCA955X_RESET_NANDF BIT(14) 7431d3d0f1fSWills Wang #define QCA955X_RESET_GE1_MAC BIT(13) 7441d3d0f1fSWills Wang #define QCA955X_RESET_SGMII_ANALOG BIT(12) 7451d3d0f1fSWills Wang #define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 7461d3d0f1fSWills Wang #define QCA955X_RESET_HOST_DMA_INT BIT(10) 7471d3d0f1fSWills Wang #define QCA955X_RESET_GE0_MAC BIT(9) 7481d3d0f1fSWills Wang #define QCA955X_RESET_SGMII BIT(8) 7491d3d0f1fSWills Wang #define QCA955X_RESET_PCIE_PHY BIT(7) 7501d3d0f1fSWills Wang #define QCA955X_RESET_PCIE BIT(6) 7511d3d0f1fSWills Wang #define QCA955X_RESET_USB_HOST BIT(5) 7521d3d0f1fSWills Wang #define QCA955X_RESET_USB_PHY BIT(4) 7531d3d0f1fSWills Wang #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 7541d3d0f1fSWills Wang #define QCA955X_RESET_LUT BIT(2) 7551d3d0f1fSWills Wang #define QCA955X_RESET_MBOX BIT(1) 7561d3d0f1fSWills Wang #define QCA955X_RESET_I2S BIT(0) 7571d3d0f1fSWills Wang 7581d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) 7591d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_DDR2 BIT(13) 7601d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) 7611d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 7621d3d0f1fSWills Wang 7631d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 7641d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 7651d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 7661d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 7671d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 7681d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 7691d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 7701d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 7711d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 7721d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 7731d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 7741d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 7751d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 7761d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 7771d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_DDR1 BIT(0) 7781d3d0f1fSWills Wang 7791d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) 7801d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) 7811d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) 7821d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) 7831d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 7841d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_DDR1 BIT(0) 7851d3d0f1fSWills Wang 7861d3d0f1fSWills Wang #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 7871d3d0f1fSWills Wang 7881d3d0f1fSWills Wang #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) 7891d3d0f1fSWills Wang 7901d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 7911d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 7921d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 7931d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 7941d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 7951d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 7961d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 7971d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 7981d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 7991d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 8001d3d0f1fSWills Wang (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 8011d3d0f1fSWills Wang AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 8021d3d0f1fSWills Wang 8031d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 8041d3d0f1fSWills Wang (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 8051d3d0f1fSWills Wang AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 8061d3d0f1fSWills Wang AR934X_PCIE_WMAC_INT_PCIE_RC3) 8071d3d0f1fSWills Wang 8081d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 8091d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) 8101d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 8111d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 8121d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) 8131d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 8141d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 8151d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 8161d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 8171d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ 8181d3d0f1fSWills Wang (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ 8191d3d0f1fSWills Wang QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) 8201d3d0f1fSWills Wang 8211d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ 8221d3d0f1fSWills Wang (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ 8231d3d0f1fSWills Wang QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ 8241d3d0f1fSWills Wang QCA953X_PCIE_WMAC_INT_PCIE_RC3) 8251d3d0f1fSWills Wang 8261d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_MISC BIT(0) 8271d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_TX BIT(1) 8281d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 8291d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 8301d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 8311d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 8321d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 8331d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 8341d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 8351d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 8361d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 8371d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 8381d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 8391d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 8401d3d0f1fSWills Wang #define QCA955X_EXT_INT_USB1 BIT(24) 8411d3d0f1fSWills Wang #define QCA955X_EXT_INT_USB2 BIT(28) 8421d3d0f1fSWills Wang 8431d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_ALL \ 8441d3d0f1fSWills Wang (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 8451d3d0f1fSWills Wang QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 8461d3d0f1fSWills Wang 8471d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_ALL \ 8481d3d0f1fSWills Wang (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 8491d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 8501d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC1_INT3) 8511d3d0f1fSWills Wang 8521d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_ALL \ 8531d3d0f1fSWills Wang (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 8541d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 8551d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC2_INT3) 8561d3d0f1fSWills Wang 8571d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_MISC BIT(0) 8581d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_TX BIT(1) 8591d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_RXLP BIT(2) 8601d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_RXHP BIT(3) 8611d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1 BIT(4) 8621d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) 8631d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) 8641d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) 8651d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) 8661d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2 BIT(12) 8671d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) 8681d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) 8691d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) 8701d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) 8711d3d0f1fSWills Wang #define QCA956X_EXT_INT_USB1 BIT(24) 8721d3d0f1fSWills Wang #define QCA956X_EXT_INT_USB2 BIT(28) 8731d3d0f1fSWills Wang 8741d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_ALL \ 8751d3d0f1fSWills Wang (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ 8761d3d0f1fSWills Wang QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) 8771d3d0f1fSWills Wang 8781d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_ALL \ 8791d3d0f1fSWills Wang (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ 8801d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ 8811d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC1_INT3) 8821d3d0f1fSWills Wang 8831d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_ALL \ 8841d3d0f1fSWills Wang (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ 8851d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ 8861d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC2_INT3) 8871d3d0f1fSWills Wang 8881d3d0f1fSWills Wang #define REV_ID_MAJOR_MASK 0xfff0 8891d3d0f1fSWills Wang #define REV_ID_MAJOR_AR71XX 0x00a0 8901d3d0f1fSWills Wang #define REV_ID_MAJOR_AR913X 0x00b0 8911d3d0f1fSWills Wang #define REV_ID_MAJOR_AR7240 0x00c0 8921d3d0f1fSWills Wang #define REV_ID_MAJOR_AR7241 0x0100 8931d3d0f1fSWills Wang #define REV_ID_MAJOR_AR7242 0x1100 8941d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9330 0x0110 8951d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9331 0x1110 8961d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9341 0x0120 8971d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9342 0x1120 8981d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9344 0x2120 8991d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9533 0x0140 9001d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9533_V2 0x0160 9011d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9556 0x0130 9021d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9558 0x1130 9031d3d0f1fSWills Wang #define REV_ID_MAJOR_TP9343 0x0150 9041d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9561 0x1150 9051d3d0f1fSWills Wang 9061d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_MASK 0x3 9071d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_AR7130 0x0 9081d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_AR7141 0x1 9091d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_AR7161 0x2 9101d3d0f1fSWills Wang #define AR913X_REV_ID_MINOR_AR9130 0x0 9111d3d0f1fSWills Wang #define AR913X_REV_ID_MINOR_AR9132 0x1 9121d3d0f1fSWills Wang 9131d3d0f1fSWills Wang #define AR71XX_REV_ID_REVISION_MASK 0x3 9141d3d0f1fSWills Wang #define AR71XX_REV_ID_REVISION_SHIFT 2 9151d3d0f1fSWills Wang #define AR71XX_REV_ID_REVISION2_MASK 0xf 9161d3d0f1fSWills Wang 9171d3d0f1fSWills Wang /* 9181d3d0f1fSWills Wang * RTC block 9191d3d0f1fSWills Wang */ 9201d3d0f1fSWills Wang #define AR933X_RTC_REG_RESET 0x40 9211d3d0f1fSWills Wang #define AR933X_RTC_REG_STATUS 0x44 9221d3d0f1fSWills Wang #define AR933X_RTC_REG_DERIVED 0x48 9231d3d0f1fSWills Wang #define AR933X_RTC_REG_FORCE_WAKE 0x4c 9241d3d0f1fSWills Wang #define AR933X_RTC_REG_INT_CAUSE 0x50 9251d3d0f1fSWills Wang #define AR933X_RTC_REG_CAUSE_CLR 0x50 9261d3d0f1fSWills Wang #define AR933X_RTC_REG_INT_ENABLE 0x54 9271d3d0f1fSWills Wang #define AR933X_RTC_REG_INT_MASKE 0x58 9281d3d0f1fSWills Wang 9291d3d0f1fSWills Wang #define QCA953X_RTC_REG_SYNC_RESET 0x40 9301d3d0f1fSWills Wang #define QCA953X_RTC_REG_SYNC_STATUS 0x44 9311d3d0f1fSWills Wang 9321d3d0f1fSWills Wang /* 9331d3d0f1fSWills Wang * SPI block 9341d3d0f1fSWills Wang */ 9351d3d0f1fSWills Wang #define AR71XX_SPI_REG_FS 0x00 9361d3d0f1fSWills Wang #define AR71XX_SPI_REG_CTRL 0x04 9371d3d0f1fSWills Wang #define AR71XX_SPI_REG_IOC 0x08 9381d3d0f1fSWills Wang #define AR71XX_SPI_REG_RDS 0x0c 9391d3d0f1fSWills Wang 9401d3d0f1fSWills Wang #define AR71XX_SPI_FS_GPIO BIT(0) 9411d3d0f1fSWills Wang 9421d3d0f1fSWills Wang #define AR71XX_SPI_CTRL_RD BIT(6) 9431d3d0f1fSWills Wang #define AR71XX_SPI_CTRL_DIV_MASK 0x3f 9441d3d0f1fSWills Wang 9451d3d0f1fSWills Wang #define AR71XX_SPI_IOC_DO BIT(0) 9461d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CLK BIT(8) 9471d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 9481d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 9491d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 9501d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 9511d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS_ALL \ 9521d3d0f1fSWills Wang (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) 9531d3d0f1fSWills Wang 9541d3d0f1fSWills Wang /* 9551d3d0f1fSWills Wang * GPIO block 9561d3d0f1fSWills Wang */ 9571d3d0f1fSWills Wang #define AR71XX_GPIO_REG_OE 0x00 9581d3d0f1fSWills Wang #define AR71XX_GPIO_REG_IN 0x04 9591d3d0f1fSWills Wang #define AR71XX_GPIO_REG_OUT 0x08 9601d3d0f1fSWills Wang #define AR71XX_GPIO_REG_SET 0x0c 9611d3d0f1fSWills Wang #define AR71XX_GPIO_REG_CLEAR 0x10 9621d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_MODE 0x14 9631d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_TYPE 0x18 9641d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 9651d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_PENDING 0x20 9661d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_ENABLE 0x24 9671d3d0f1fSWills Wang #define AR71XX_GPIO_REG_FUNC 0x28 9681d3d0f1fSWills Wang #define AR933X_GPIO_REG_FUNC 0x30 9691d3d0f1fSWills Wang 9701d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC0 0x2c 9711d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC1 0x30 9721d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC2 0x34 9731d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC3 0x38 9741d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC4 0x3c 9751d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC5 0x40 9761d3d0f1fSWills Wang #define AR934X_GPIO_REG_FUNC 0x6c 9771d3d0f1fSWills Wang 9781d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC0 0x2c 9791d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC1 0x30 9801d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC2 0x34 9811d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC3 0x38 9821d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC4 0x3c 9831d3d0f1fSWills Wang #define QCA953X_GPIO_REG_IN_ENABLE0 0x44 9841d3d0f1fSWills Wang #define QCA953X_GPIO_REG_FUNC 0x6c 9851d3d0f1fSWills Wang 9861d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c 9871d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC1 0x30 9881d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC2 0x34 9891d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC3 0x38 9901d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c 9911d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 9921d3d0f1fSWills Wang #define QCA955X_GPIO_REG_FUNC 0x6c 9931d3d0f1fSWills Wang 9941d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c 9951d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC1 0x30 9961d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC2 0x34 9971d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC3 0x38 9981d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC4 0x3c 9991d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC5 0x40 10001d3d0f1fSWills Wang #define QCA956X_GPIO_REG_IN_ENABLE0 0x44 10011d3d0f1fSWills Wang #define QCA956X_GPIO_REG_IN_ENABLE3 0x50 10021d3d0f1fSWills Wang #define QCA956X_GPIO_REG_FUNC 0x6c 10031d3d0f1fSWills Wang 10041d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) 10051d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) 10061d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) 10071d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) 10081d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_UART_EN BIT(8) 10091d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) 10101d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) 10111d3d0f1fSWills Wang 10121d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) 10131d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_SPI_EN BIT(18) 10141d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 10151d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 10161d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) 10171d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) 10181d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) 10191d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) 10201d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) 10211d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 10221d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 10231d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 10241d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 10251d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 10261d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 10271d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_UART_EN BIT(1) 10281d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) 10291d3d0f1fSWills Wang 10301d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) 10311d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) 10321d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) 10331d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) 10341d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S1_EN BIT(18) 10351d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S0_EN BIT(17) 10361d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_SLIC_EN BIT(16) 10371d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) 10381d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_UART_EN BIT(8) 10391d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) 10401d3d0f1fSWills Wang 10411d3d0f1fSWills Wang #define AR933X_GPIO(x) BIT(x) 10421d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) 10431d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) 10441d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) 10451d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) 10461d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_I2SO_EN BIT(26) 10471d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) 10481d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) 10491d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) 10501d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPI_EN BIT(18) 10511d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_RES_TRUE BIT(15) 10521d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 10531d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 10541d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_XLNA_EN BIT(12) 10551d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 10561d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 10571d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 10581d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 10591d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 10601d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 10611d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_UART_EN BIT(1) 10621d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) 10631d3d0f1fSWills Wang 10641d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) 10651d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) 10661d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) 10671d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) 10681d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) 10691d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) 10701d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) 10711d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) 10721d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) 10731d3d0f1fSWills Wang 10741d3d0f1fSWills Wang #define AR934X_GPIO_OUT_GPIO 0 10751d3d0f1fSWills Wang #define AR934X_GPIO_OUT_SPI_CS1 7 10761d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK0 41 10771d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK1 42 10781d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK2 43 10791d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK3 44 10801d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK4 45 10811d3d0f1fSWills Wang #define AR934X_GPIO_OUT_EXT_LNA0 46 10821d3d0f1fSWills Wang #define AR934X_GPIO_OUT_EXT_LNA1 47 10831d3d0f1fSWills Wang 10841d3d0f1fSWills Wang #define QCA953X_GPIO(x) BIT(x) 10851d3d0f1fSWills Wang #define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) 10861d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 10871d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 10881d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 10891d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 10901d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 10911d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 10921d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 10931d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 10941d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 10951d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 10961d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 10971d3d0f1fSWills Wang 10981d3d0f1fSWills Wang #define QCA953X_GPIO_IN_MUX_UART0_SIN 9 10991d3d0f1fSWills Wang #define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 11001d3d0f1fSWills Wang 11011d3d0f1fSWills Wang #define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 11021d3d0f1fSWills Wang #define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 11031d3d0f1fSWills Wang 11041d3d0f1fSWills Wang #define AR71XX_GPIO_COUNT 16 11051d3d0f1fSWills Wang #define AR7240_GPIO_COUNT 18 11061d3d0f1fSWills Wang #define AR7241_GPIO_COUNT 20 11071d3d0f1fSWills Wang #define AR913X_GPIO_COUNT 22 11081d3d0f1fSWills Wang #define AR933X_GPIO_COUNT 30 11091d3d0f1fSWills Wang #define AR934X_GPIO_COUNT 23 11101d3d0f1fSWills Wang #define QCA953X_GPIO_COUNT 18 11111d3d0f1fSWills Wang #define QCA955X_GPIO_COUNT 24 11121d3d0f1fSWills Wang #define QCA956X_GPIO_COUNT 23 11131d3d0f1fSWills Wang 11141d3d0f1fSWills Wang /* 11151d3d0f1fSWills Wang * SRIF block 11161d3d0f1fSWills Wang */ 11171d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL1_REG 0x240 11181d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL2_REG 0x244 11191d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL3_REG 0x248 11201d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL4_REG 0x24c 11211d3d0f1fSWills Wang 11221d3d0f1fSWills Wang #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 11231d3d0f1fSWills Wang #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 11241d3d0f1fSWills Wang #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 1125*e08539b7SMarek Vasut #define AR934X_SRIF_CPU_DPLL4_REG 0x1cc 11261d3d0f1fSWills Wang 11271d3d0f1fSWills Wang #define AR934X_SRIF_DDR_DPLL1_REG 0x240 11281d3d0f1fSWills Wang #define AR934X_SRIF_DDR_DPLL2_REG 0x244 11291d3d0f1fSWills Wang #define AR934X_SRIF_DDR_DPLL3_REG 0x248 1130*e08539b7SMarek Vasut #define AR934X_SRIF_DDR_DPLL4_REG 0x24c 11311d3d0f1fSWills Wang 11321d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 11331d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f 11341d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_NINT_SHIFT 18 11351d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff 11361d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 11371d3d0f1fSWills Wang 11381d3d0f1fSWills Wang #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) 11391d3d0f1fSWills Wang #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 11401d3d0f1fSWills Wang #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 11411d3d0f1fSWills Wang 11421d3d0f1fSWills Wang #define QCA953X_SRIF_BB_DPLL1_REG 0x180 11431d3d0f1fSWills Wang #define QCA953X_SRIF_BB_DPLL2_REG 0x184 11441d3d0f1fSWills Wang #define QCA953X_SRIF_BB_DPLL3_REG 0x188 11451d3d0f1fSWills Wang 11461d3d0f1fSWills Wang #define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 11471d3d0f1fSWills Wang #define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 11481d3d0f1fSWills Wang #define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 11491d3d0f1fSWills Wang 11501d3d0f1fSWills Wang #define QCA953X_SRIF_DDR_DPLL1_REG 0x240 11511d3d0f1fSWills Wang #define QCA953X_SRIF_DDR_DPLL2_REG 0x244 11521d3d0f1fSWills Wang #define QCA953X_SRIF_DDR_DPLL3_REG 0x248 11531d3d0f1fSWills Wang 11541d3d0f1fSWills Wang #define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 11551d3d0f1fSWills Wang #define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 11561d3d0f1fSWills Wang #define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 11571d3d0f1fSWills Wang 11581d3d0f1fSWills Wang #define QCA953X_SRIF_PMU1_REG 0xc40 11591d3d0f1fSWills Wang #define QCA953X_SRIF_PMU2_REG 0xc44 11601d3d0f1fSWills Wang 11611d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 11621d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f 11631d3d0f1fSWills Wang 11641d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 11651d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff 11661d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 11671d3d0f1fSWills Wang 11681d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) 11691d3d0f1fSWills Wang 11701d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KI_SHIFT 29 11711d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KI_MASK 0x3 11721d3d0f1fSWills Wang 11731d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KD_SHIFT 25 11741d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KD_MASK 0xf 11751d3d0f1fSWills Wang 11761d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_PWD BIT(22) 11771d3d0f1fSWills Wang 11781d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 11791d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 11801d3d0f1fSWills Wang 11811d3d0f1fSWills Wang /* 11821d3d0f1fSWills Wang * MII_CTRL block 11831d3d0f1fSWills Wang */ 11841d3d0f1fSWills Wang #define AR71XX_MII_REG_MII0_CTRL 0x00 11851d3d0f1fSWills Wang #define AR71XX_MII_REG_MII1_CTRL 0x04 11861d3d0f1fSWills Wang 11871d3d0f1fSWills Wang #define AR71XX_MII_CTRL_IF_MASK 3 11881d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_SHIFT 4 11891d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_MASK 3 11901d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_10 0 11911d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_100 1 11921d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_1000 2 11931d3d0f1fSWills Wang 11941d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_GMII 0 11951d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_MII 1 11961d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_RGMII 2 11971d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_RMII 3 11981d3d0f1fSWills Wang 11991d3d0f1fSWills Wang #define AR71XX_MII1_CTRL_IF_RGMII 0 12001d3d0f1fSWills Wang #define AR71XX_MII1_CTRL_IF_RMII 1 12011d3d0f1fSWills Wang 12021d3d0f1fSWills Wang /* 12031d3d0f1fSWills Wang * AR933X GMAC interface 12041d3d0f1fSWills Wang */ 12051d3d0f1fSWills Wang #define AR933X_GMAC_REG_ETH_CFG 0x00 12061d3d0f1fSWills Wang 12071d3d0f1fSWills Wang #define AR933X_ETH_CFG_RGMII_GE0 BIT(0) 12081d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0 BIT(1) 12091d3d0f1fSWills Wang #define AR933X_ETH_CFG_GMII_GE0 BIT(2) 12101d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) 12111d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) 12121d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) 12131d3d0f1fSWills Wang #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) 12141d3d0f1fSWills Wang #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 12151d3d0f1fSWills Wang #define AR933X_ETH_CFG_RMII_GE0 BIT(9) 12161d3d0f1fSWills Wang #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 12171d3d0f1fSWills Wang #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) 12181d3d0f1fSWills Wang 12191d3d0f1fSWills Wang /* 12201d3d0f1fSWills Wang * AR934X GMAC Interface 12211d3d0f1fSWills Wang */ 12221d3d0f1fSWills Wang #define AR934X_GMAC_REG_ETH_CFG 0x00 12231d3d0f1fSWills Wang 12241d3d0f1fSWills Wang #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) 12251d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0 BIT(1) 12261d3d0f1fSWills Wang #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) 12271d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) 12281d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) 12291d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) 12301d3d0f1fSWills Wang #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) 12311d3d0f1fSWills Wang #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) 12321d3d0f1fSWills Wang #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) 12331d3d0f1fSWills Wang #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) 12341d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) 12351d3d0f1fSWills Wang #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) 12361d3d0f1fSWills Wang #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 12371d3d0f1fSWills Wang #define AR934X_ETH_CFG_RXD_DELAY BIT(14) 12381d3d0f1fSWills Wang #define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 12391d3d0f1fSWills Wang #define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 12401d3d0f1fSWills Wang #define AR934X_ETH_CFG_RDV_DELAY BIT(16) 12411d3d0f1fSWills Wang #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 12421d3d0f1fSWills Wang #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 12431d3d0f1fSWills Wang 12441d3d0f1fSWills Wang /* 12451d3d0f1fSWills Wang * QCA953X GMAC Interface 12461d3d0f1fSWills Wang */ 12471d3d0f1fSWills Wang #define QCA953X_GMAC_REG_ETH_CFG 0x00 12481d3d0f1fSWills Wang 12491d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) 12501d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) 12511d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) 12521d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 12531d3d0f1fSWills Wang 12541d3d0f1fSWills Wang /* 12551d3d0f1fSWills Wang * QCA955X GMAC Interface 12561d3d0f1fSWills Wang */ 12571d3d0f1fSWills Wang 12581d3d0f1fSWills Wang #define QCA955X_GMAC_REG_ETH_CFG 0x00 12591d3d0f1fSWills Wang 12601d3d0f1fSWills Wang #define QCA955X_ETH_CFG_RGMII_EN BIT(0) 12611d3d0f1fSWills Wang #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 12621d3d0f1fSWills Wang 12631d3d0f1fSWills Wang #endif /* __ASM_AR71XX_H */ 1264