1*1d3d0f1fSWills Wang /* 2*1d3d0f1fSWills Wang * Atheros AR71XX/AR724X/AR913X SoC register definitions 3*1d3d0f1fSWills Wang * 4*1d3d0f1fSWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 5*1d3d0f1fSWills Wang * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 6*1d3d0f1fSWills Wang * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 7*1d3d0f1fSWills Wang * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8*1d3d0f1fSWills Wang * 9*1d3d0f1fSWills Wang * SPDX-License-Identifier: GPL-2.0+ 10*1d3d0f1fSWills Wang */ 11*1d3d0f1fSWills Wang 12*1d3d0f1fSWills Wang #ifndef __ASM_MACH_AR71XX_REGS_H 13*1d3d0f1fSWills Wang #define __ASM_MACH_AR71XX_REGS_H 14*1d3d0f1fSWills Wang 15*1d3d0f1fSWills Wang #ifndef __ASSEMBLY__ 16*1d3d0f1fSWills Wang #include <linux/bitops.h> 17*1d3d0f1fSWills Wang #else 18*1d3d0f1fSWills Wang #ifndef BIT 19*1d3d0f1fSWills Wang #define BIT(nr) (1 << (nr)) 20*1d3d0f1fSWills Wang #endif 21*1d3d0f1fSWills Wang #endif 22*1d3d0f1fSWills Wang 23*1d3d0f1fSWills Wang #define AR71XX_APB_BASE 0x18000000 24*1d3d0f1fSWills Wang #define AR71XX_GE0_BASE 0x19000000 25*1d3d0f1fSWills Wang #define AR71XX_GE0_SIZE 0x10000 26*1d3d0f1fSWills Wang #define AR71XX_GE1_BASE 0x1a000000 27*1d3d0f1fSWills Wang #define AR71XX_GE1_SIZE 0x10000 28*1d3d0f1fSWills Wang #define AR71XX_EHCI_BASE 0x1b000000 29*1d3d0f1fSWills Wang #define AR71XX_EHCI_SIZE 0x1000 30*1d3d0f1fSWills Wang #define AR71XX_OHCI_BASE 0x1c000000 31*1d3d0f1fSWills Wang #define AR71XX_OHCI_SIZE 0x1000 32*1d3d0f1fSWills Wang #define AR71XX_SPI_BASE 0x1f000000 33*1d3d0f1fSWills Wang #define AR71XX_SPI_SIZE 0x01000000 34*1d3d0f1fSWills Wang 35*1d3d0f1fSWills Wang #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) 36*1d3d0f1fSWills Wang #define AR71XX_DDR_CTRL_SIZE 0x100 37*1d3d0f1fSWills Wang #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 38*1d3d0f1fSWills Wang #define AR71XX_UART_SIZE 0x100 39*1d3d0f1fSWills Wang #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 40*1d3d0f1fSWills Wang #define AR71XX_USB_CTRL_SIZE 0x100 41*1d3d0f1fSWills Wang #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 42*1d3d0f1fSWills Wang #define AR71XX_GPIO_SIZE 0x100 43*1d3d0f1fSWills Wang #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 44*1d3d0f1fSWills Wang #define AR71XX_PLL_SIZE 0x100 45*1d3d0f1fSWills Wang #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 46*1d3d0f1fSWills Wang #define AR71XX_RESET_SIZE 0x100 47*1d3d0f1fSWills Wang #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) 48*1d3d0f1fSWills Wang #define AR71XX_MII_SIZE 0x100 49*1d3d0f1fSWills Wang 50*1d3d0f1fSWills Wang #define AR71XX_PCI_MEM_BASE 0x10000000 51*1d3d0f1fSWills Wang #define AR71XX_PCI_MEM_SIZE 0x07000000 52*1d3d0f1fSWills Wang 53*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN0_OFFS 0x10000000 54*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN1_OFFS 0x11000000 55*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN2_OFFS 0x12000000 56*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN3_OFFS 0x13000000 57*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN4_OFFS 0x14000000 58*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN5_OFFS 0x15000000 59*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN6_OFFS 0x16000000 60*1d3d0f1fSWills Wang #define AR71XX_PCI_WIN7_OFFS 0x07000000 61*1d3d0f1fSWills Wang 62*1d3d0f1fSWills Wang #define AR71XX_PCI_CFG_BASE \ 63*1d3d0f1fSWills Wang (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) 64*1d3d0f1fSWills Wang #define AR71XX_PCI_CFG_SIZE 0x100 65*1d3d0f1fSWills Wang 66*1d3d0f1fSWills Wang #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 67*1d3d0f1fSWills Wang #define AR7240_USB_CTRL_SIZE 0x100 68*1d3d0f1fSWills Wang #define AR7240_OHCI_BASE 0x1b000000 69*1d3d0f1fSWills Wang #define AR7240_OHCI_SIZE 0x1000 70*1d3d0f1fSWills Wang 71*1d3d0f1fSWills Wang #define AR724X_PCI_MEM_BASE 0x10000000 72*1d3d0f1fSWills Wang #define AR724X_PCI_MEM_SIZE 0x04000000 73*1d3d0f1fSWills Wang 74*1d3d0f1fSWills Wang #define AR724X_PCI_CFG_BASE 0x14000000 75*1d3d0f1fSWills Wang #define AR724X_PCI_CFG_SIZE 0x1000 76*1d3d0f1fSWills Wang #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) 77*1d3d0f1fSWills Wang #define AR724X_PCI_CRP_SIZE 0x1000 78*1d3d0f1fSWills Wang #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) 79*1d3d0f1fSWills Wang #define AR724X_PCI_CTRL_SIZE 0x100 80*1d3d0f1fSWills Wang 81*1d3d0f1fSWills Wang #define AR724X_EHCI_BASE 0x1b000000 82*1d3d0f1fSWills Wang #define AR724X_EHCI_SIZE 0x1000 83*1d3d0f1fSWills Wang 84*1d3d0f1fSWills Wang #define AR913X_EHCI_BASE 0x1b000000 85*1d3d0f1fSWills Wang #define AR913X_EHCI_SIZE 0x1000 86*1d3d0f1fSWills Wang #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 87*1d3d0f1fSWills Wang #define AR913X_WMAC_SIZE 0x30000 88*1d3d0f1fSWills Wang 89*1d3d0f1fSWills Wang #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) 90*1d3d0f1fSWills Wang #define AR933X_UART_SIZE 0x14 91*1d3d0f1fSWills Wang #define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 92*1d3d0f1fSWills Wang #define AR933X_GMAC_SIZE 0x04 93*1d3d0f1fSWills Wang #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 94*1d3d0f1fSWills Wang #define AR933X_WMAC_SIZE 0x20000 95*1d3d0f1fSWills Wang #define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) 96*1d3d0f1fSWills Wang #define AR933X_RTC_SIZE 0x1000 97*1d3d0f1fSWills Wang #define AR933X_EHCI_BASE 0x1b000000 98*1d3d0f1fSWills Wang #define AR933X_EHCI_SIZE 0x1000 99*1d3d0f1fSWills Wang #define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) 100*1d3d0f1fSWills Wang #define AR933X_SRIF_SIZE 0x1000 101*1d3d0f1fSWills Wang 102*1d3d0f1fSWills Wang #define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 103*1d3d0f1fSWills Wang #define AR934X_GMAC_SIZE 0x14 104*1d3d0f1fSWills Wang #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 105*1d3d0f1fSWills Wang #define AR934X_WMAC_SIZE 0x20000 106*1d3d0f1fSWills Wang #define AR934X_EHCI_BASE 0x1b000000 107*1d3d0f1fSWills Wang #define AR934X_EHCI_SIZE 0x200 108*1d3d0f1fSWills Wang #define AR934X_NFC_BASE 0x1b000200 109*1d3d0f1fSWills Wang #define AR934X_NFC_SIZE 0xb8 110*1d3d0f1fSWills Wang #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) 111*1d3d0f1fSWills Wang #define AR934X_SRIF_SIZE 0x1000 112*1d3d0f1fSWills Wang 113*1d3d0f1fSWills Wang #define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 114*1d3d0f1fSWills Wang #define QCA953X_GMAC_SIZE 0x14 115*1d3d0f1fSWills Wang #define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 116*1d3d0f1fSWills Wang #define QCA953X_WMAC_SIZE 0x20000 117*1d3d0f1fSWills Wang #define QCA953X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) 118*1d3d0f1fSWills Wang #define QCA953X_RTC_SIZE 0x1000 119*1d3d0f1fSWills Wang #define QCA953X_EHCI_BASE 0x1b000000 120*1d3d0f1fSWills Wang #define QCA953X_EHCI_SIZE 0x200 121*1d3d0f1fSWills Wang #define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) 122*1d3d0f1fSWills Wang #define QCA953X_SRIF_SIZE 0x1000 123*1d3d0f1fSWills Wang 124*1d3d0f1fSWills Wang #define QCA953X_PCI_CFG_BASE0 0x14000000 125*1d3d0f1fSWills Wang #define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) 126*1d3d0f1fSWills Wang #define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) 127*1d3d0f1fSWills Wang #define QCA953X_PCI_MEM_BASE0 0x10000000 128*1d3d0f1fSWills Wang #define QCA953X_PCI_MEM_SIZE 0x02000000 129*1d3d0f1fSWills Wang 130*1d3d0f1fSWills Wang #define QCA955X_PCI_MEM_BASE0 0x10000000 131*1d3d0f1fSWills Wang #define QCA955X_PCI_MEM_BASE1 0x12000000 132*1d3d0f1fSWills Wang #define QCA955X_PCI_MEM_SIZE 0x02000000 133*1d3d0f1fSWills Wang #define QCA955X_PCI_CFG_BASE0 0x14000000 134*1d3d0f1fSWills Wang #define QCA955X_PCI_CFG_BASE1 0x16000000 135*1d3d0f1fSWills Wang #define QCA955X_PCI_CFG_SIZE 0x1000 136*1d3d0f1fSWills Wang #define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) 137*1d3d0f1fSWills Wang #define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) 138*1d3d0f1fSWills Wang #define QCA955X_PCI_CRP_SIZE 0x1000 139*1d3d0f1fSWills Wang #define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) 140*1d3d0f1fSWills Wang #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) 141*1d3d0f1fSWills Wang #define QCA955X_PCI_CTRL_SIZE 0x100 142*1d3d0f1fSWills Wang 143*1d3d0f1fSWills Wang #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 144*1d3d0f1fSWills Wang #define QCA955X_GMAC_SIZE 0x40 145*1d3d0f1fSWills Wang #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 146*1d3d0f1fSWills Wang #define QCA955X_WMAC_SIZE 0x20000 147*1d3d0f1fSWills Wang #define QCA955X_EHCI0_BASE 0x1b000000 148*1d3d0f1fSWills Wang #define QCA955X_EHCI1_BASE 0x1b400000 149*1d3d0f1fSWills Wang #define QCA955X_EHCI_SIZE 0x1000 150*1d3d0f1fSWills Wang #define QCA955X_NFC_BASE 0x1b800200 151*1d3d0f1fSWills Wang #define QCA955X_NFC_SIZE 0xb8 152*1d3d0f1fSWills Wang 153*1d3d0f1fSWills Wang #define QCA956X_PCI_MEM_BASE1 0x12000000 154*1d3d0f1fSWills Wang #define QCA956X_PCI_MEM_SIZE 0x02000000 155*1d3d0f1fSWills Wang #define QCA956X_PCI_CFG_BASE1 0x16000000 156*1d3d0f1fSWills Wang #define QCA956X_PCI_CFG_SIZE 0x1000 157*1d3d0f1fSWills Wang #define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) 158*1d3d0f1fSWills Wang #define QCA956X_PCI_CRP_SIZE 0x1000 159*1d3d0f1fSWills Wang #define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) 160*1d3d0f1fSWills Wang #define QCA956X_PCI_CTRL_SIZE 0x100 161*1d3d0f1fSWills Wang 162*1d3d0f1fSWills Wang #define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 163*1d3d0f1fSWills Wang #define QCA956X_WMAC_SIZE 0x20000 164*1d3d0f1fSWills Wang #define QCA956X_EHCI0_BASE 0x1b000000 165*1d3d0f1fSWills Wang #define QCA956X_EHCI1_BASE 0x1b400000 166*1d3d0f1fSWills Wang #define QCA956X_EHCI_SIZE 0x200 167*1d3d0f1fSWills Wang #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 168*1d3d0f1fSWills Wang #define QCA956X_GMAC_SIZE 0x64 169*1d3d0f1fSWills Wang 170*1d3d0f1fSWills Wang /* 171*1d3d0f1fSWills Wang * DDR_CTRL block 172*1d3d0f1fSWills Wang */ 173*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_CONFIG 0x00 174*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_CONFIG2 0x04 175*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_MODE 0x08 176*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_EMR 0x0c 177*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_CONTROL 0x10 178*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_REFRESH 0x14 179*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_RD_CYCLE 0x18 180*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_TAP_CTRL0 0x1c 181*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_TAP_CTRL1 0x20 182*1d3d0f1fSWills Wang 183*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN0 0x7c 184*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN1 0x80 185*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN2 0x84 186*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN3 0x88 187*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN4 0x8c 188*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN5 0x90 189*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN6 0x94 190*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_PCI_WIN7 0x98 191*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_GE0 0x9c 192*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 193*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_USB 0xa4 194*1d3d0f1fSWills Wang #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 195*1d3d0f1fSWills Wang 196*1d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_GE0 0x7c 197*1d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_GE1 0x80 198*1d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_USB 0x84 199*1d3d0f1fSWills Wang #define AR724X_DDR_REG_FLUSH_PCIE 0x88 200*1d3d0f1fSWills Wang 201*1d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_GE0 0x7c 202*1d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_GE1 0x80 203*1d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_USB 0x84 204*1d3d0f1fSWills Wang #define AR913X_DDR_REG_FLUSH_WMAC 0x88 205*1d3d0f1fSWills Wang 206*1d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_GE0 0x7c 207*1d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_GE1 0x80 208*1d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_USB 0x84 209*1d3d0f1fSWills Wang #define AR933X_DDR_REG_FLUSH_WMAC 0x88 210*1d3d0f1fSWills Wang #define AR933X_DDR_REG_DDR2_CONFIG 0x8c 211*1d3d0f1fSWills Wang #define AR933X_DDR_REG_EMR2 0x90 212*1d3d0f1fSWills Wang #define AR933X_DDR_REG_EMR3 0x94 213*1d3d0f1fSWills Wang #define AR933X_DDR_REG_BURST 0x98 214*1d3d0f1fSWills Wang #define AR933X_DDR_REG_TIMEOUT_MAX 0x9c 215*1d3d0f1fSWills Wang #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c 216*1d3d0f1fSWills Wang #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c 217*1d3d0f1fSWills Wang 218*1d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_GE0 0x9c 219*1d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_GE1 0xa0 220*1d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_USB 0xa4 221*1d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 222*1d3d0f1fSWills Wang #define AR934X_DDR_REG_FLUSH_WMAC 0xac 223*1d3d0f1fSWills Wang 224*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_GE0 0x9c 225*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_GE1 0xa0 226*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_USB 0xa4 227*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 228*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_FLUSH_WMAC 0xac 229*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 230*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_BURST 0xc4 231*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_BURST2 0xc8 232*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc 233*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_CTL_CONF 0x108 234*1d3d0f1fSWills Wang #define QCA953X_DDR_REG_CONFIG3 0x15c 235*1d3d0f1fSWills Wang 236*1d3d0f1fSWills Wang /* 237*1d3d0f1fSWills Wang * PLL block 238*1d3d0f1fSWills Wang */ 239*1d3d0f1fSWills Wang #define AR71XX_PLL_REG_CPU_CONFIG 0x00 240*1d3d0f1fSWills Wang #define AR71XX_PLL_REG_SEC_CONFIG 0x04 241*1d3d0f1fSWills Wang #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 242*1d3d0f1fSWills Wang #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 243*1d3d0f1fSWills Wang 244*1d3d0f1fSWills Wang #define AR71XX_PLL_DIV_SHIFT 3 245*1d3d0f1fSWills Wang #define AR71XX_PLL_DIV_MASK 0x1f 246*1d3d0f1fSWills Wang #define AR71XX_CPU_DIV_SHIFT 16 247*1d3d0f1fSWills Wang #define AR71XX_CPU_DIV_MASK 0x3 248*1d3d0f1fSWills Wang #define AR71XX_DDR_DIV_SHIFT 18 249*1d3d0f1fSWills Wang #define AR71XX_DDR_DIV_MASK 0x3 250*1d3d0f1fSWills Wang #define AR71XX_AHB_DIV_SHIFT 20 251*1d3d0f1fSWills Wang #define AR71XX_AHB_DIV_MASK 0x7 252*1d3d0f1fSWills Wang 253*1d3d0f1fSWills Wang #define AR71XX_ETH0_PLL_SHIFT 17 254*1d3d0f1fSWills Wang #define AR71XX_ETH1_PLL_SHIFT 19 255*1d3d0f1fSWills Wang 256*1d3d0f1fSWills Wang #define AR724X_PLL_REG_CPU_CONFIG 0x00 257*1d3d0f1fSWills Wang #define AR724X_PLL_REG_PCIE_CONFIG 0x18 258*1d3d0f1fSWills Wang 259*1d3d0f1fSWills Wang #define AR724X_PLL_DIV_SHIFT 0 260*1d3d0f1fSWills Wang #define AR724X_PLL_DIV_MASK 0x3ff 261*1d3d0f1fSWills Wang #define AR724X_PLL_REF_DIV_SHIFT 10 262*1d3d0f1fSWills Wang #define AR724X_PLL_REF_DIV_MASK 0xf 263*1d3d0f1fSWills Wang #define AR724X_AHB_DIV_SHIFT 19 264*1d3d0f1fSWills Wang #define AR724X_AHB_DIV_MASK 0x1 265*1d3d0f1fSWills Wang #define AR724X_DDR_DIV_SHIFT 22 266*1d3d0f1fSWills Wang #define AR724X_DDR_DIV_MASK 0x3 267*1d3d0f1fSWills Wang 268*1d3d0f1fSWills Wang #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c 269*1d3d0f1fSWills Wang 270*1d3d0f1fSWills Wang #define AR913X_PLL_REG_CPU_CONFIG 0x00 271*1d3d0f1fSWills Wang #define AR913X_PLL_REG_ETH_CONFIG 0x04 272*1d3d0f1fSWills Wang #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 273*1d3d0f1fSWills Wang #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 274*1d3d0f1fSWills Wang 275*1d3d0f1fSWills Wang #define AR913X_PLL_DIV_SHIFT 0 276*1d3d0f1fSWills Wang #define AR913X_PLL_DIV_MASK 0x3ff 277*1d3d0f1fSWills Wang #define AR913X_DDR_DIV_SHIFT 22 278*1d3d0f1fSWills Wang #define AR913X_DDR_DIV_MASK 0x3 279*1d3d0f1fSWills Wang #define AR913X_AHB_DIV_SHIFT 19 280*1d3d0f1fSWills Wang #define AR913X_AHB_DIV_MASK 0x1 281*1d3d0f1fSWills Wang 282*1d3d0f1fSWills Wang #define AR913X_ETH0_PLL_SHIFT 20 283*1d3d0f1fSWills Wang #define AR913X_ETH1_PLL_SHIFT 22 284*1d3d0f1fSWills Wang 285*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_REG 0x00 286*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_REG 0x08 287*1d3d0f1fSWills Wang #define AR933X_PLL_DITHER_FRAC_REG 0x10 288*1d3d0f1fSWills Wang 289*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 290*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 291*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 292*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 293*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 294*1d3d0f1fSWills Wang #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 295*1d3d0f1fSWills Wang 296*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) 297*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 298*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 299*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 300*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 301*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 302*1d3d0f1fSWills Wang #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 303*1d3d0f1fSWills Wang 304*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_REG 0x00 305*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_REG 0x04 306*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 307*1d3d0f1fSWills Wang #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 308*1d3d0f1fSWills Wang #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c 309*1d3d0f1fSWills Wang 310*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 311*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 312*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 313*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 314*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 315*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 316*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 317*1d3d0f1fSWills Wang #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 318*1d3d0f1fSWills Wang 319*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 320*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 321*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 322*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 323*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 324*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 325*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 326*1d3d0f1fSWills Wang #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 327*1d3d0f1fSWills Wang 328*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 329*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 330*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 331*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 332*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 333*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 334*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 335*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 336*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 337*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 338*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 339*1d3d0f1fSWills Wang #define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 340*1d3d0f1fSWills Wang 341*1d3d0f1fSWills Wang #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) 342*1d3d0f1fSWills Wang 343*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_REG 0x00 344*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_REG 0x04 345*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_REG 0x08 346*1d3d0f1fSWills Wang #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 347*1d3d0f1fSWills Wang #define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c 348*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 349*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 350*1d3d0f1fSWills Wang 351*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 352*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 353*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 354*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f 355*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 356*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 357*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 358*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 359*1d3d0f1fSWills Wang 360*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 361*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 362*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 363*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f 364*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 365*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 366*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 367*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 368*1d3d0f1fSWills Wang 369*1d3d0f1fSWills Wang #define QCA953X_PLL_CONFIG_PWD BIT(30) 370*1d3d0f1fSWills Wang 371*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 372*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 373*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 374*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 375*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 376*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 377*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 378*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 379*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 380*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 381*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 382*1d3d0f1fSWills Wang #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 383*1d3d0f1fSWills Wang 384*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 385*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 386*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 387*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 388*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 389*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 390*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 391*1d3d0f1fSWills Wang #define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 392*1d3d0f1fSWills Wang 393*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 394*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 395*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 396*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 397*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 398*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 399*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 400*1d3d0f1fSWills Wang #define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 401*1d3d0f1fSWills Wang 402*1d3d0f1fSWills Wang #define QCA953X_PLL_DIT_FRAC_EN BIT(31) 403*1d3d0f1fSWills Wang 404*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_REG 0x00 405*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_REG 0x04 406*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_REG 0x08 407*1d3d0f1fSWills Wang #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 408*1d3d0f1fSWills Wang #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 409*1d3d0f1fSWills Wang 410*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 411*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 412*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 413*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 414*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 415*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 416*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 417*1d3d0f1fSWills Wang #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 418*1d3d0f1fSWills Wang 419*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 420*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 421*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 422*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 423*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 424*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 425*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 426*1d3d0f1fSWills Wang #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 427*1d3d0f1fSWills Wang 428*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 429*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 430*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 431*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 432*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 433*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 434*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 435*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 436*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 437*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 438*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 439*1d3d0f1fSWills Wang #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 440*1d3d0f1fSWills Wang 441*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_REG 0x00 442*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 443*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_REG 0x08 444*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c 445*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_REG 0x10 446*1d3d0f1fSWills Wang 447*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 448*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 449*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 450*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 451*1d3d0f1fSWills Wang 452*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 453*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f 454*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 455*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff 456*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 457*1d3d0f1fSWills Wang #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff 458*1d3d0f1fSWills Wang 459*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 460*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 461*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 462*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 463*1d3d0f1fSWills Wang 464*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 465*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f 466*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 467*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff 468*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 469*1d3d0f1fSWills Wang #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff 470*1d3d0f1fSWills Wang 471*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 472*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 473*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 474*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 475*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 476*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 477*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 478*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 479*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 480*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) 481*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) 482*1d3d0f1fSWills Wang #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 483*1d3d0f1fSWills Wang 484*1d3d0f1fSWills Wang /* 485*1d3d0f1fSWills Wang * USB_CONFIG block 486*1d3d0f1fSWills Wang */ 487*1d3d0f1fSWills Wang #define AR71XX_USB_CTRL_REG_FLADJ 0x00 488*1d3d0f1fSWills Wang #define AR71XX_USB_CTRL_REG_CONFIG 0x04 489*1d3d0f1fSWills Wang 490*1d3d0f1fSWills Wang /* 491*1d3d0f1fSWills Wang * RESET block 492*1d3d0f1fSWills Wang */ 493*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_TIMER 0x00 494*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 495*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_WDOG_CTRL 0x08 496*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_WDOG 0x0c 497*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 498*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 499*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 500*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 501*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 502*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_RESET_MODULE 0x24 503*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_PERFC_CTRL 0x2c 504*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_PERFC0 0x30 505*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_PERFC1 0x34 506*1d3d0f1fSWills Wang #define AR71XX_RESET_REG_REV_ID 0x90 507*1d3d0f1fSWills Wang 508*1d3d0f1fSWills Wang #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 509*1d3d0f1fSWills Wang #define AR913X_RESET_REG_RESET_MODULE 0x1c 510*1d3d0f1fSWills Wang #define AR913X_RESET_REG_PERF_CTRL 0x20 511*1d3d0f1fSWills Wang #define AR913X_RESET_REG_PERFC0 0x24 512*1d3d0f1fSWills Wang #define AR913X_RESET_REG_PERFC1 0x28 513*1d3d0f1fSWills Wang 514*1d3d0f1fSWills Wang #define AR724X_RESET_REG_RESET_MODULE 0x1c 515*1d3d0f1fSWills Wang 516*1d3d0f1fSWills Wang #define AR933X_RESET_REG_RESET_MODULE 0x1c 517*1d3d0f1fSWills Wang #define AR933X_RESET_REG_BOOTSTRAP 0xac 518*1d3d0f1fSWills Wang 519*1d3d0f1fSWills Wang #define AR934X_RESET_REG_RESET_MODULE 0x1c 520*1d3d0f1fSWills Wang #define AR934X_RESET_REG_BOOTSTRAP 0xb0 521*1d3d0f1fSWills Wang #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 522*1d3d0f1fSWills Wang 523*1d3d0f1fSWills Wang #define QCA953X_RESET_REG_RESET_MODULE 0x1c 524*1d3d0f1fSWills Wang #define QCA953X_RESET_REG_BOOTSTRAP 0xb0 525*1d3d0f1fSWills Wang #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 526*1d3d0f1fSWills Wang 527*1d3d0f1fSWills Wang #define QCA955X_RESET_REG_RESET_MODULE 0x1c 528*1d3d0f1fSWills Wang #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 529*1d3d0f1fSWills Wang #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac 530*1d3d0f1fSWills Wang 531*1d3d0f1fSWills Wang #define QCA956X_RESET_REG_RESET_MODULE 0x1c 532*1d3d0f1fSWills Wang #define QCA956X_RESET_REG_BOOTSTRAP 0xb0 533*1d3d0f1fSWills Wang #define QCA956X_RESET_REG_EXT_INT_STATUS 0xac 534*1d3d0f1fSWills Wang 535*1d3d0f1fSWills Wang #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) 536*1d3d0f1fSWills Wang #define MISC_INT_ETHSW BIT(12) 537*1d3d0f1fSWills Wang #define MISC_INT_TIMER4 BIT(10) 538*1d3d0f1fSWills Wang #define MISC_INT_TIMER3 BIT(9) 539*1d3d0f1fSWills Wang #define MISC_INT_TIMER2 BIT(8) 540*1d3d0f1fSWills Wang #define MISC_INT_DMA BIT(7) 541*1d3d0f1fSWills Wang #define MISC_INT_OHCI BIT(6) 542*1d3d0f1fSWills Wang #define MISC_INT_PERFC BIT(5) 543*1d3d0f1fSWills Wang #define MISC_INT_WDOG BIT(4) 544*1d3d0f1fSWills Wang #define MISC_INT_UART BIT(3) 545*1d3d0f1fSWills Wang #define MISC_INT_GPIO BIT(2) 546*1d3d0f1fSWills Wang #define MISC_INT_ERROR BIT(1) 547*1d3d0f1fSWills Wang #define MISC_INT_TIMER BIT(0) 548*1d3d0f1fSWills Wang 549*1d3d0f1fSWills Wang #define AR71XX_RESET_EXTERNAL BIT(28) 550*1d3d0f1fSWills Wang #define AR71XX_RESET_FULL_CHIP BIT(24) 551*1d3d0f1fSWills Wang #define AR71XX_RESET_CPU_NMI BIT(21) 552*1d3d0f1fSWills Wang #define AR71XX_RESET_CPU_COLD BIT(20) 553*1d3d0f1fSWills Wang #define AR71XX_RESET_DMA BIT(19) 554*1d3d0f1fSWills Wang #define AR71XX_RESET_SLIC BIT(18) 555*1d3d0f1fSWills Wang #define AR71XX_RESET_STEREO BIT(17) 556*1d3d0f1fSWills Wang #define AR71XX_RESET_DDR BIT(16) 557*1d3d0f1fSWills Wang #define AR71XX_RESET_GE1_MAC BIT(13) 558*1d3d0f1fSWills Wang #define AR71XX_RESET_GE1_PHY BIT(12) 559*1d3d0f1fSWills Wang #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 560*1d3d0f1fSWills Wang #define AR71XX_RESET_GE0_MAC BIT(9) 561*1d3d0f1fSWills Wang #define AR71XX_RESET_GE0_PHY BIT(8) 562*1d3d0f1fSWills Wang #define AR71XX_RESET_USB_OHCI_DLL BIT(6) 563*1d3d0f1fSWills Wang #define AR71XX_RESET_USB_HOST BIT(5) 564*1d3d0f1fSWills Wang #define AR71XX_RESET_USB_PHY BIT(4) 565*1d3d0f1fSWills Wang #define AR71XX_RESET_PCI_BUS BIT(1) 566*1d3d0f1fSWills Wang #define AR71XX_RESET_PCI_CORE BIT(0) 567*1d3d0f1fSWills Wang 568*1d3d0f1fSWills Wang #define AR7240_RESET_USB_HOST BIT(5) 569*1d3d0f1fSWills Wang #define AR7240_RESET_OHCI_DLL BIT(3) 570*1d3d0f1fSWills Wang 571*1d3d0f1fSWills Wang #define AR724X_RESET_GE1_MDIO BIT(23) 572*1d3d0f1fSWills Wang #define AR724X_RESET_GE0_MDIO BIT(22) 573*1d3d0f1fSWills Wang #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 574*1d3d0f1fSWills Wang #define AR724X_RESET_PCIE_PHY BIT(7) 575*1d3d0f1fSWills Wang #define AR724X_RESET_PCIE BIT(6) 576*1d3d0f1fSWills Wang #define AR724X_RESET_USB_HOST BIT(5) 577*1d3d0f1fSWills Wang #define AR724X_RESET_USB_PHY BIT(4) 578*1d3d0f1fSWills Wang #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 579*1d3d0f1fSWills Wang 580*1d3d0f1fSWills Wang #define AR913X_RESET_AMBA2WMAC BIT(22) 581*1d3d0f1fSWills Wang #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 582*1d3d0f1fSWills Wang #define AR913X_RESET_USB_HOST BIT(5) 583*1d3d0f1fSWills Wang #define AR913X_RESET_USB_PHY BIT(4) 584*1d3d0f1fSWills Wang 585*1d3d0f1fSWills Wang #define AR933X_RESET_GE1_MDIO BIT(23) 586*1d3d0f1fSWills Wang #define AR933X_RESET_GE0_MDIO BIT(22) 587*1d3d0f1fSWills Wang #define AR933X_RESET_GE1_MAC BIT(13) 588*1d3d0f1fSWills Wang #define AR933X_RESET_WMAC BIT(11) 589*1d3d0f1fSWills Wang #define AR933X_RESET_GE0_MAC BIT(9) 590*1d3d0f1fSWills Wang #define AR933X_RESET_USB_HOST BIT(5) 591*1d3d0f1fSWills Wang #define AR933X_RESET_USB_PHY BIT(4) 592*1d3d0f1fSWills Wang #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 593*1d3d0f1fSWills Wang 594*1d3d0f1fSWills Wang #define AR934X_RESET_HOST BIT(31) 595*1d3d0f1fSWills Wang #define AR934X_RESET_SLIC BIT(30) 596*1d3d0f1fSWills Wang #define AR934X_RESET_HDMA BIT(29) 597*1d3d0f1fSWills Wang #define AR934X_RESET_EXTERNAL BIT(28) 598*1d3d0f1fSWills Wang #define AR934X_RESET_RTC BIT(27) 599*1d3d0f1fSWills Wang #define AR934X_RESET_PCIE_EP_INT BIT(26) 600*1d3d0f1fSWills Wang #define AR934X_RESET_CHKSUM_ACC BIT(25) 601*1d3d0f1fSWills Wang #define AR934X_RESET_FULL_CHIP BIT(24) 602*1d3d0f1fSWills Wang #define AR934X_RESET_GE1_MDIO BIT(23) 603*1d3d0f1fSWills Wang #define AR934X_RESET_GE0_MDIO BIT(22) 604*1d3d0f1fSWills Wang #define AR934X_RESET_CPU_NMI BIT(21) 605*1d3d0f1fSWills Wang #define AR934X_RESET_CPU_COLD BIT(20) 606*1d3d0f1fSWills Wang #define AR934X_RESET_HOST_RESET_INT BIT(19) 607*1d3d0f1fSWills Wang #define AR934X_RESET_PCIE_EP BIT(18) 608*1d3d0f1fSWills Wang #define AR934X_RESET_UART1 BIT(17) 609*1d3d0f1fSWills Wang #define AR934X_RESET_DDR BIT(16) 610*1d3d0f1fSWills Wang #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 611*1d3d0f1fSWills Wang #define AR934X_RESET_NANDF BIT(14) 612*1d3d0f1fSWills Wang #define AR934X_RESET_GE1_MAC BIT(13) 613*1d3d0f1fSWills Wang #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) 614*1d3d0f1fSWills Wang #define AR934X_RESET_USB_PHY_ANALOG BIT(11) 615*1d3d0f1fSWills Wang #define AR934X_RESET_HOST_DMA_INT BIT(10) 616*1d3d0f1fSWills Wang #define AR934X_RESET_GE0_MAC BIT(9) 617*1d3d0f1fSWills Wang #define AR934X_RESET_ETH_SWITCH BIT(8) 618*1d3d0f1fSWills Wang #define AR934X_RESET_PCIE_PHY BIT(7) 619*1d3d0f1fSWills Wang #define AR934X_RESET_PCIE BIT(6) 620*1d3d0f1fSWills Wang #define AR934X_RESET_USB_HOST BIT(5) 621*1d3d0f1fSWills Wang #define AR934X_RESET_USB_PHY BIT(4) 622*1d3d0f1fSWills Wang #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 623*1d3d0f1fSWills Wang #define AR934X_RESET_LUT BIT(2) 624*1d3d0f1fSWills Wang #define AR934X_RESET_MBOX BIT(1) 625*1d3d0f1fSWills Wang #define AR934X_RESET_I2S BIT(0) 626*1d3d0f1fSWills Wang 627*1d3d0f1fSWills Wang #define QCA953X_RESET_USB_EXT_PWR BIT(29) 628*1d3d0f1fSWills Wang #define QCA953X_RESET_EXTERNAL BIT(28) 629*1d3d0f1fSWills Wang #define QCA953X_RESET_RTC BIT(27) 630*1d3d0f1fSWills Wang #define QCA953X_RESET_FULL_CHIP BIT(24) 631*1d3d0f1fSWills Wang #define QCA953X_RESET_GE1_MDIO BIT(23) 632*1d3d0f1fSWills Wang #define QCA953X_RESET_GE0_MDIO BIT(22) 633*1d3d0f1fSWills Wang #define QCA953X_RESET_CPU_NMI BIT(21) 634*1d3d0f1fSWills Wang #define QCA953X_RESET_CPU_COLD BIT(20) 635*1d3d0f1fSWills Wang #define QCA953X_RESET_DDR BIT(16) 636*1d3d0f1fSWills Wang #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 637*1d3d0f1fSWills Wang #define QCA953X_RESET_GE1_MAC BIT(13) 638*1d3d0f1fSWills Wang #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) 639*1d3d0f1fSWills Wang #define QCA953X_RESET_USB_PHY_ANALOG BIT(11) 640*1d3d0f1fSWills Wang #define QCA953X_RESET_GE0_MAC BIT(9) 641*1d3d0f1fSWills Wang #define QCA953X_RESET_ETH_SWITCH BIT(8) 642*1d3d0f1fSWills Wang #define QCA953X_RESET_PCIE_PHY BIT(7) 643*1d3d0f1fSWills Wang #define QCA953X_RESET_PCIE BIT(6) 644*1d3d0f1fSWills Wang #define QCA953X_RESET_USB_HOST BIT(5) 645*1d3d0f1fSWills Wang #define QCA953X_RESET_USB_PHY BIT(4) 646*1d3d0f1fSWills Wang #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) 647*1d3d0f1fSWills Wang 648*1d3d0f1fSWills Wang #define QCA955X_RESET_HOST BIT(31) 649*1d3d0f1fSWills Wang #define QCA955X_RESET_SLIC BIT(30) 650*1d3d0f1fSWills Wang #define QCA955X_RESET_HDMA BIT(29) 651*1d3d0f1fSWills Wang #define QCA955X_RESET_EXTERNAL BIT(28) 652*1d3d0f1fSWills Wang #define QCA955X_RESET_RTC BIT(27) 653*1d3d0f1fSWills Wang #define QCA955X_RESET_PCIE_EP_INT BIT(26) 654*1d3d0f1fSWills Wang #define QCA955X_RESET_CHKSUM_ACC BIT(25) 655*1d3d0f1fSWills Wang #define QCA955X_RESET_FULL_CHIP BIT(24) 656*1d3d0f1fSWills Wang #define QCA955X_RESET_GE1_MDIO BIT(23) 657*1d3d0f1fSWills Wang #define QCA955X_RESET_GE0_MDIO BIT(22) 658*1d3d0f1fSWills Wang #define QCA955X_RESET_CPU_NMI BIT(21) 659*1d3d0f1fSWills Wang #define QCA955X_RESET_CPU_COLD BIT(20) 660*1d3d0f1fSWills Wang #define QCA955X_RESET_HOST_RESET_INT BIT(19) 661*1d3d0f1fSWills Wang #define QCA955X_RESET_PCIE_EP BIT(18) 662*1d3d0f1fSWills Wang #define QCA955X_RESET_UART1 BIT(17) 663*1d3d0f1fSWills Wang #define QCA955X_RESET_DDR BIT(16) 664*1d3d0f1fSWills Wang #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 665*1d3d0f1fSWills Wang #define QCA955X_RESET_NANDF BIT(14) 666*1d3d0f1fSWills Wang #define QCA955X_RESET_GE1_MAC BIT(13) 667*1d3d0f1fSWills Wang #define QCA955X_RESET_SGMII_ANALOG BIT(12) 668*1d3d0f1fSWills Wang #define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 669*1d3d0f1fSWills Wang #define QCA955X_RESET_HOST_DMA_INT BIT(10) 670*1d3d0f1fSWills Wang #define QCA955X_RESET_GE0_MAC BIT(9) 671*1d3d0f1fSWills Wang #define QCA955X_RESET_SGMII BIT(8) 672*1d3d0f1fSWills Wang #define QCA955X_RESET_PCIE_PHY BIT(7) 673*1d3d0f1fSWills Wang #define QCA955X_RESET_PCIE BIT(6) 674*1d3d0f1fSWills Wang #define QCA955X_RESET_USB_HOST BIT(5) 675*1d3d0f1fSWills Wang #define QCA955X_RESET_USB_PHY BIT(4) 676*1d3d0f1fSWills Wang #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 677*1d3d0f1fSWills Wang #define QCA955X_RESET_LUT BIT(2) 678*1d3d0f1fSWills Wang #define QCA955X_RESET_MBOX BIT(1) 679*1d3d0f1fSWills Wang #define QCA955X_RESET_I2S BIT(0) 680*1d3d0f1fSWills Wang 681*1d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) 682*1d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_DDR2 BIT(13) 683*1d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) 684*1d3d0f1fSWills Wang #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 685*1d3d0f1fSWills Wang 686*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 687*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 688*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 689*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 690*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 691*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 692*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 693*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 694*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 695*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 696*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 697*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 698*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 699*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 700*1d3d0f1fSWills Wang #define AR934X_BOOTSTRAP_DDR1 BIT(0) 701*1d3d0f1fSWills Wang 702*1d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) 703*1d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) 704*1d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) 705*1d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) 706*1d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 707*1d3d0f1fSWills Wang #define QCA953X_BOOTSTRAP_DDR1 BIT(0) 708*1d3d0f1fSWills Wang 709*1d3d0f1fSWills Wang #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 710*1d3d0f1fSWills Wang 711*1d3d0f1fSWills Wang #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) 712*1d3d0f1fSWills Wang 713*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 714*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 715*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 716*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 717*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 718*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 719*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 720*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 721*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 722*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 723*1d3d0f1fSWills Wang (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 724*1d3d0f1fSWills Wang AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 725*1d3d0f1fSWills Wang 726*1d3d0f1fSWills Wang #define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 727*1d3d0f1fSWills Wang (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 728*1d3d0f1fSWills Wang AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 729*1d3d0f1fSWills Wang AR934X_PCIE_WMAC_INT_PCIE_RC3) 730*1d3d0f1fSWills Wang 731*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 732*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) 733*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 734*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 735*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) 736*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 737*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 738*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 739*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 740*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ 741*1d3d0f1fSWills Wang (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ 742*1d3d0f1fSWills Wang QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) 743*1d3d0f1fSWills Wang 744*1d3d0f1fSWills Wang #define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ 745*1d3d0f1fSWills Wang (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ 746*1d3d0f1fSWills Wang QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ 747*1d3d0f1fSWills Wang QCA953X_PCIE_WMAC_INT_PCIE_RC3) 748*1d3d0f1fSWills Wang 749*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_MISC BIT(0) 750*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_TX BIT(1) 751*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 752*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 753*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 754*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 755*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 756*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 757*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 758*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 759*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 760*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 761*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 762*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 763*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_USB1 BIT(24) 764*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_USB2 BIT(28) 765*1d3d0f1fSWills Wang 766*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_WMAC_ALL \ 767*1d3d0f1fSWills Wang (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 768*1d3d0f1fSWills Wang QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 769*1d3d0f1fSWills Wang 770*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC1_ALL \ 771*1d3d0f1fSWills Wang (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 772*1d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 773*1d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC1_INT3) 774*1d3d0f1fSWills Wang 775*1d3d0f1fSWills Wang #define QCA955X_EXT_INT_PCIE_RC2_ALL \ 776*1d3d0f1fSWills Wang (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 777*1d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 778*1d3d0f1fSWills Wang QCA955X_EXT_INT_PCIE_RC2_INT3) 779*1d3d0f1fSWills Wang 780*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_MISC BIT(0) 781*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_TX BIT(1) 782*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_RXLP BIT(2) 783*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_RXHP BIT(3) 784*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1 BIT(4) 785*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) 786*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) 787*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) 788*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) 789*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2 BIT(12) 790*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) 791*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) 792*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) 793*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) 794*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_USB1 BIT(24) 795*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_USB2 BIT(28) 796*1d3d0f1fSWills Wang 797*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_WMAC_ALL \ 798*1d3d0f1fSWills Wang (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ 799*1d3d0f1fSWills Wang QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) 800*1d3d0f1fSWills Wang 801*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC1_ALL \ 802*1d3d0f1fSWills Wang (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ 803*1d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ 804*1d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC1_INT3) 805*1d3d0f1fSWills Wang 806*1d3d0f1fSWills Wang #define QCA956X_EXT_INT_PCIE_RC2_ALL \ 807*1d3d0f1fSWills Wang (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ 808*1d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ 809*1d3d0f1fSWills Wang QCA956X_EXT_INT_PCIE_RC2_INT3) 810*1d3d0f1fSWills Wang 811*1d3d0f1fSWills Wang #define REV_ID_MAJOR_MASK 0xfff0 812*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR71XX 0x00a0 813*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR913X 0x00b0 814*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR7240 0x00c0 815*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR7241 0x0100 816*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR7242 0x1100 817*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9330 0x0110 818*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9331 0x1110 819*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9341 0x0120 820*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9342 0x1120 821*1d3d0f1fSWills Wang #define REV_ID_MAJOR_AR9344 0x2120 822*1d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9533 0x0140 823*1d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9533_V2 0x0160 824*1d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9556 0x0130 825*1d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9558 0x1130 826*1d3d0f1fSWills Wang #define REV_ID_MAJOR_TP9343 0x0150 827*1d3d0f1fSWills Wang #define REV_ID_MAJOR_QCA9561 0x1150 828*1d3d0f1fSWills Wang 829*1d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_MASK 0x3 830*1d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_AR7130 0x0 831*1d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_AR7141 0x1 832*1d3d0f1fSWills Wang #define AR71XX_REV_ID_MINOR_AR7161 0x2 833*1d3d0f1fSWills Wang #define AR913X_REV_ID_MINOR_AR9130 0x0 834*1d3d0f1fSWills Wang #define AR913X_REV_ID_MINOR_AR9132 0x1 835*1d3d0f1fSWills Wang 836*1d3d0f1fSWills Wang #define AR71XX_REV_ID_REVISION_MASK 0x3 837*1d3d0f1fSWills Wang #define AR71XX_REV_ID_REVISION_SHIFT 2 838*1d3d0f1fSWills Wang #define AR71XX_REV_ID_REVISION2_MASK 0xf 839*1d3d0f1fSWills Wang 840*1d3d0f1fSWills Wang /* 841*1d3d0f1fSWills Wang * RTC block 842*1d3d0f1fSWills Wang */ 843*1d3d0f1fSWills Wang #define AR933X_RTC_REG_RESET 0x40 844*1d3d0f1fSWills Wang #define AR933X_RTC_REG_STATUS 0x44 845*1d3d0f1fSWills Wang #define AR933X_RTC_REG_DERIVED 0x48 846*1d3d0f1fSWills Wang #define AR933X_RTC_REG_FORCE_WAKE 0x4c 847*1d3d0f1fSWills Wang #define AR933X_RTC_REG_INT_CAUSE 0x50 848*1d3d0f1fSWills Wang #define AR933X_RTC_REG_CAUSE_CLR 0x50 849*1d3d0f1fSWills Wang #define AR933X_RTC_REG_INT_ENABLE 0x54 850*1d3d0f1fSWills Wang #define AR933X_RTC_REG_INT_MASKE 0x58 851*1d3d0f1fSWills Wang 852*1d3d0f1fSWills Wang #define QCA953X_RTC_REG_SYNC_RESET 0x40 853*1d3d0f1fSWills Wang #define QCA953X_RTC_REG_SYNC_STATUS 0x44 854*1d3d0f1fSWills Wang 855*1d3d0f1fSWills Wang /* 856*1d3d0f1fSWills Wang * SPI block 857*1d3d0f1fSWills Wang */ 858*1d3d0f1fSWills Wang #define AR71XX_SPI_REG_FS 0x00 859*1d3d0f1fSWills Wang #define AR71XX_SPI_REG_CTRL 0x04 860*1d3d0f1fSWills Wang #define AR71XX_SPI_REG_IOC 0x08 861*1d3d0f1fSWills Wang #define AR71XX_SPI_REG_RDS 0x0c 862*1d3d0f1fSWills Wang 863*1d3d0f1fSWills Wang #define AR71XX_SPI_FS_GPIO BIT(0) 864*1d3d0f1fSWills Wang 865*1d3d0f1fSWills Wang #define AR71XX_SPI_CTRL_RD BIT(6) 866*1d3d0f1fSWills Wang #define AR71XX_SPI_CTRL_DIV_MASK 0x3f 867*1d3d0f1fSWills Wang 868*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_DO BIT(0) 869*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CLK BIT(8) 870*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 871*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 872*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 873*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 874*1d3d0f1fSWills Wang #define AR71XX_SPI_IOC_CS_ALL \ 875*1d3d0f1fSWills Wang (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) 876*1d3d0f1fSWills Wang 877*1d3d0f1fSWills Wang /* 878*1d3d0f1fSWills Wang * GPIO block 879*1d3d0f1fSWills Wang */ 880*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_OE 0x00 881*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_IN 0x04 882*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_OUT 0x08 883*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_SET 0x0c 884*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_CLEAR 0x10 885*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_MODE 0x14 886*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_TYPE 0x18 887*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 888*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_PENDING 0x20 889*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_INT_ENABLE 0x24 890*1d3d0f1fSWills Wang #define AR71XX_GPIO_REG_FUNC 0x28 891*1d3d0f1fSWills Wang #define AR933X_GPIO_REG_FUNC 0x30 892*1d3d0f1fSWills Wang 893*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC0 0x2c 894*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC1 0x30 895*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC2 0x34 896*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC3 0x38 897*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC4 0x3c 898*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_OUT_FUNC5 0x40 899*1d3d0f1fSWills Wang #define AR934X_GPIO_REG_FUNC 0x6c 900*1d3d0f1fSWills Wang 901*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC0 0x2c 902*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC1 0x30 903*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC2 0x34 904*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC3 0x38 905*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_OUT_FUNC4 0x3c 906*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_IN_ENABLE0 0x44 907*1d3d0f1fSWills Wang #define QCA953X_GPIO_REG_FUNC 0x6c 908*1d3d0f1fSWills Wang 909*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c 910*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC1 0x30 911*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC2 0x34 912*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC3 0x38 913*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c 914*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 915*1d3d0f1fSWills Wang #define QCA955X_GPIO_REG_FUNC 0x6c 916*1d3d0f1fSWills Wang 917*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c 918*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC1 0x30 919*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC2 0x34 920*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC3 0x38 921*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC4 0x3c 922*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_OUT_FUNC5 0x40 923*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_IN_ENABLE0 0x44 924*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_IN_ENABLE3 0x50 925*1d3d0f1fSWills Wang #define QCA956X_GPIO_REG_FUNC 0x6c 926*1d3d0f1fSWills Wang 927*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) 928*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) 929*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) 930*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) 931*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_UART_EN BIT(8) 932*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) 933*1d3d0f1fSWills Wang #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) 934*1d3d0f1fSWills Wang 935*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) 936*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_SPI_EN BIT(18) 937*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 938*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 939*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) 940*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) 941*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) 942*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) 943*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) 944*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 945*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 946*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 947*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 948*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 949*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 950*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_UART_EN BIT(1) 951*1d3d0f1fSWills Wang #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) 952*1d3d0f1fSWills Wang 953*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) 954*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) 955*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) 956*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) 957*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S1_EN BIT(18) 958*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_I2S0_EN BIT(17) 959*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_SLIC_EN BIT(16) 960*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) 961*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_UART_EN BIT(8) 962*1d3d0f1fSWills Wang #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) 963*1d3d0f1fSWills Wang 964*1d3d0f1fSWills Wang #define AR933X_GPIO(x) BIT(x) 965*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) 966*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) 967*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) 968*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) 969*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_I2SO_EN BIT(26) 970*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) 971*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) 972*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) 973*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPI_EN BIT(18) 974*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_RES_TRUE BIT(15) 975*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 976*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 977*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_XLNA_EN BIT(12) 978*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 979*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 980*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 981*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 982*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 983*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 984*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_UART_EN BIT(1) 985*1d3d0f1fSWills Wang #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) 986*1d3d0f1fSWills Wang 987*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) 988*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) 989*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) 990*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) 991*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) 992*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) 993*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) 994*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) 995*1d3d0f1fSWills Wang #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) 996*1d3d0f1fSWills Wang 997*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_GPIO 0 998*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_SPI_CS1 7 999*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK0 41 1000*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK1 42 1001*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK2 43 1002*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK3 44 1003*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_LED_LINK4 45 1004*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_EXT_LNA0 46 1005*1d3d0f1fSWills Wang #define AR934X_GPIO_OUT_EXT_LNA1 47 1006*1d3d0f1fSWills Wang 1007*1d3d0f1fSWills Wang #define QCA953X_GPIO(x) BIT(x) 1008*1d3d0f1fSWills Wang #define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) 1009*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 1010*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 1011*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 1012*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 1013*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 1014*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 1015*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 1016*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 1017*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 1018*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 1019*1d3d0f1fSWills Wang #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 1020*1d3d0f1fSWills Wang 1021*1d3d0f1fSWills Wang #define QCA953X_GPIO_IN_MUX_UART0_SIN 9 1022*1d3d0f1fSWills Wang #define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 1023*1d3d0f1fSWills Wang 1024*1d3d0f1fSWills Wang #define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 1025*1d3d0f1fSWills Wang #define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 1026*1d3d0f1fSWills Wang 1027*1d3d0f1fSWills Wang #define AR71XX_GPIO_COUNT 16 1028*1d3d0f1fSWills Wang #define AR7240_GPIO_COUNT 18 1029*1d3d0f1fSWills Wang #define AR7241_GPIO_COUNT 20 1030*1d3d0f1fSWills Wang #define AR913X_GPIO_COUNT 22 1031*1d3d0f1fSWills Wang #define AR933X_GPIO_COUNT 30 1032*1d3d0f1fSWills Wang #define AR934X_GPIO_COUNT 23 1033*1d3d0f1fSWills Wang #define QCA953X_GPIO_COUNT 18 1034*1d3d0f1fSWills Wang #define QCA955X_GPIO_COUNT 24 1035*1d3d0f1fSWills Wang #define QCA956X_GPIO_COUNT 23 1036*1d3d0f1fSWills Wang 1037*1d3d0f1fSWills Wang /* 1038*1d3d0f1fSWills Wang * SRIF block 1039*1d3d0f1fSWills Wang */ 1040*1d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL1_REG 0x240 1041*1d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL2_REG 0x244 1042*1d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL3_REG 0x248 1043*1d3d0f1fSWills Wang #define AR933X_SRIF_DDR_DPLL4_REG 0x24c 1044*1d3d0f1fSWills Wang 1045*1d3d0f1fSWills Wang #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 1046*1d3d0f1fSWills Wang #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 1047*1d3d0f1fSWills Wang #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 1048*1d3d0f1fSWills Wang 1049*1d3d0f1fSWills Wang #define AR934X_SRIF_DDR_DPLL1_REG 0x240 1050*1d3d0f1fSWills Wang #define AR934X_SRIF_DDR_DPLL2_REG 0x244 1051*1d3d0f1fSWills Wang #define AR934X_SRIF_DDR_DPLL3_REG 0x248 1052*1d3d0f1fSWills Wang 1053*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 1054*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f 1055*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_NINT_SHIFT 18 1056*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff 1057*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1058*1d3d0f1fSWills Wang 1059*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1060*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 1061*1d3d0f1fSWills Wang #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 1062*1d3d0f1fSWills Wang 1063*1d3d0f1fSWills Wang #define QCA953X_SRIF_BB_DPLL1_REG 0x180 1064*1d3d0f1fSWills Wang #define QCA953X_SRIF_BB_DPLL2_REG 0x184 1065*1d3d0f1fSWills Wang #define QCA953X_SRIF_BB_DPLL3_REG 0x188 1066*1d3d0f1fSWills Wang 1067*1d3d0f1fSWills Wang #define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 1068*1d3d0f1fSWills Wang #define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 1069*1d3d0f1fSWills Wang #define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 1070*1d3d0f1fSWills Wang 1071*1d3d0f1fSWills Wang #define QCA953X_SRIF_DDR_DPLL1_REG 0x240 1072*1d3d0f1fSWills Wang #define QCA953X_SRIF_DDR_DPLL2_REG 0x244 1073*1d3d0f1fSWills Wang #define QCA953X_SRIF_DDR_DPLL3_REG 0x248 1074*1d3d0f1fSWills Wang 1075*1d3d0f1fSWills Wang #define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 1076*1d3d0f1fSWills Wang #define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 1077*1d3d0f1fSWills Wang #define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 1078*1d3d0f1fSWills Wang 1079*1d3d0f1fSWills Wang #define QCA953X_SRIF_PMU1_REG 0xc40 1080*1d3d0f1fSWills Wang #define QCA953X_SRIF_PMU2_REG 0xc44 1081*1d3d0f1fSWills Wang 1082*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 1083*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f 1084*1d3d0f1fSWills Wang 1085*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 1086*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff 1087*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1088*1d3d0f1fSWills Wang 1089*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1090*1d3d0f1fSWills Wang 1091*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KI_SHIFT 29 1092*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KI_MASK 0x3 1093*1d3d0f1fSWills Wang 1094*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KD_SHIFT 25 1095*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_KD_MASK 0xf 1096*1d3d0f1fSWills Wang 1097*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_PWD BIT(22) 1098*1d3d0f1fSWills Wang 1099*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 1100*1d3d0f1fSWills Wang #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 1101*1d3d0f1fSWills Wang 1102*1d3d0f1fSWills Wang /* 1103*1d3d0f1fSWills Wang * MII_CTRL block 1104*1d3d0f1fSWills Wang */ 1105*1d3d0f1fSWills Wang #define AR71XX_MII_REG_MII0_CTRL 0x00 1106*1d3d0f1fSWills Wang #define AR71XX_MII_REG_MII1_CTRL 0x04 1107*1d3d0f1fSWills Wang 1108*1d3d0f1fSWills Wang #define AR71XX_MII_CTRL_IF_MASK 3 1109*1d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_SHIFT 4 1110*1d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_MASK 3 1111*1d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_10 0 1112*1d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_100 1 1113*1d3d0f1fSWills Wang #define AR71XX_MII_CTRL_SPEED_1000 2 1114*1d3d0f1fSWills Wang 1115*1d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_GMII 0 1116*1d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_MII 1 1117*1d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_RGMII 2 1118*1d3d0f1fSWills Wang #define AR71XX_MII0_CTRL_IF_RMII 3 1119*1d3d0f1fSWills Wang 1120*1d3d0f1fSWills Wang #define AR71XX_MII1_CTRL_IF_RGMII 0 1121*1d3d0f1fSWills Wang #define AR71XX_MII1_CTRL_IF_RMII 1 1122*1d3d0f1fSWills Wang 1123*1d3d0f1fSWills Wang /* 1124*1d3d0f1fSWills Wang * AR933X GMAC interface 1125*1d3d0f1fSWills Wang */ 1126*1d3d0f1fSWills Wang #define AR933X_GMAC_REG_ETH_CFG 0x00 1127*1d3d0f1fSWills Wang 1128*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_RGMII_GE0 BIT(0) 1129*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0 BIT(1) 1130*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_GMII_GE0 BIT(2) 1131*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) 1132*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) 1133*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) 1134*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) 1135*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 1136*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_RMII_GE0 BIT(9) 1137*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 1138*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) 1139*1d3d0f1fSWills Wang 1140*1d3d0f1fSWills Wang /* 1141*1d3d0f1fSWills Wang * AR934X GMAC Interface 1142*1d3d0f1fSWills Wang */ 1143*1d3d0f1fSWills Wang #define AR934X_GMAC_REG_ETH_CFG 0x00 1144*1d3d0f1fSWills Wang 1145*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) 1146*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0 BIT(1) 1147*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) 1148*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) 1149*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) 1150*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) 1151*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) 1152*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) 1153*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) 1154*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) 1155*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) 1156*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) 1157*1d3d0f1fSWills Wang #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1158*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RXD_DELAY BIT(14) 1159*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 1160*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 1161*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RDV_DELAY BIT(16) 1162*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 1163*1d3d0f1fSWills Wang #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 1164*1d3d0f1fSWills Wang 1165*1d3d0f1fSWills Wang /* 1166*1d3d0f1fSWills Wang * QCA953X GMAC Interface 1167*1d3d0f1fSWills Wang */ 1168*1d3d0f1fSWills Wang #define QCA953X_GMAC_REG_ETH_CFG 0x00 1169*1d3d0f1fSWills Wang 1170*1d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) 1171*1d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) 1172*1d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) 1173*1d3d0f1fSWills Wang #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1174*1d3d0f1fSWills Wang 1175*1d3d0f1fSWills Wang /* 1176*1d3d0f1fSWills Wang * QCA955X GMAC Interface 1177*1d3d0f1fSWills Wang */ 1178*1d3d0f1fSWills Wang 1179*1d3d0f1fSWills Wang #define QCA955X_GMAC_REG_ETH_CFG 0x00 1180*1d3d0f1fSWills Wang 1181*1d3d0f1fSWills Wang #define QCA955X_ETH_CFG_RGMII_EN BIT(0) 1182*1d3d0f1fSWills Wang #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 1183*1d3d0f1fSWills Wang 1184*1d3d0f1fSWills Wang #endif /* __ASM_AR71XX_H */ 1185