1 /* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/addrspace.h> 10 #include <asm/types.h> 11 #include <mach/ath79.h> 12 #include <mach/ar71xx_regs.h> 13 14 struct ath79_soc_desc { 15 enum ath79_soc_type soc; 16 const char *chip; 17 int major; 18 int minor; 19 }; 20 21 static struct ath79_soc_desc desc[] = { 22 {ATH79_SOC_AR7130, "7130", 23 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130}, 24 {ATH79_SOC_AR7141, "7141", 25 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141}, 26 {ATH79_SOC_AR7161, "7161", 27 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161}, 28 {ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0}, 29 {ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0}, 30 {ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0}, 31 {ATH79_SOC_AR9130, "9130", 32 REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130}, 33 {ATH79_SOC_AR9132, "9132", 34 REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132}, 35 {ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0}, 36 {ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0}, 37 {ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0}, 38 {ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0}, 39 {ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0}, 40 {ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0}, 41 {ATH79_SOC_QCA9533, "9533", 42 REV_ID_MAJOR_QCA9533_V2, 0}, 43 {ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0}, 44 {ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0}, 45 {ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0}, 46 {ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0}, 47 }; 48 49 int arch_cpu_init(void) 50 { 51 void __iomem *base; 52 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; 53 u32 id, major, minor = 0; 54 u32 rev = 0, ver = 1; 55 int i; 56 57 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 58 MAP_NOCACHE); 59 60 id = readl(base + AR71XX_RESET_REG_REV_ID); 61 major = id & REV_ID_MAJOR_MASK; 62 switch (major) { 63 case REV_ID_MAJOR_AR71XX: 64 case REV_ID_MAJOR_AR913X: 65 minor = id & AR71XX_REV_ID_MINOR_MASK; 66 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 67 rev &= AR71XX_REV_ID_REVISION_MASK; 68 break; 69 70 case REV_ID_MAJOR_QCA9533_V2: 71 ver = 2; 72 /* drop through */ 73 74 case REV_ID_MAJOR_AR9341: 75 case REV_ID_MAJOR_AR9342: 76 case REV_ID_MAJOR_AR9344: 77 case REV_ID_MAJOR_QCA9533: 78 case REV_ID_MAJOR_QCA9556: 79 case REV_ID_MAJOR_QCA9558: 80 case REV_ID_MAJOR_TP9343: 81 case REV_ID_MAJOR_QCA9561: 82 rev = id & AR71XX_REV_ID_REVISION2_MASK; 83 break; 84 default: 85 rev = id & AR71XX_REV_ID_REVISION_MASK; 86 break; 87 } 88 89 for (i = 0; i < ARRAY_SIZE(desc); i++) { 90 if ((desc[i].major == major) && 91 (desc[i].minor == minor)) { 92 soc = desc[i].soc; 93 break; 94 } 95 } 96 97 gd->arch.id = id; 98 gd->arch.soc = soc; 99 gd->arch.rev = rev; 100 gd->arch.ver = ver; 101 return 0; 102 } 103 104 int print_cpuinfo(void) 105 { 106 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; 107 const char *chip = "????"; 108 u32 id, rev, ver; 109 int i; 110 111 for (i = 0; i < ARRAY_SIZE(desc); i++) { 112 if (desc[i].soc == gd->arch.soc) { 113 chip = desc[i].chip; 114 soc = desc[i].soc; 115 break; 116 } 117 } 118 119 id = gd->arch.id; 120 rev = gd->arch.rev; 121 ver = gd->arch.ver; 122 123 switch (soc) { 124 case ATH79_SOC_QCA9533: 125 case ATH79_SOC_QCA9556: 126 case ATH79_SOC_QCA9558: 127 case ATH79_SOC_QCA9561: 128 printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, 129 ver, rev); 130 break; 131 case ATH79_SOC_TP9343: 132 printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); 133 break; 134 case ATH79_SOC_UNKNOWN: 135 printf("ATH79: unknown SoC, id:0x%08x", id); 136 break; 137 default: 138 printf("Atheros AR%s rev %u\n", chip, rev); 139 } 140 141 return 0; 142 } 143