1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/addrspace.h> 9 #include <asm/types.h> 10 #include <mach/ath79.h> 11 #include <mach/ar71xx_regs.h> 12 13 struct ath79_soc_desc { 14 const enum ath79_soc_type soc; 15 const char *chip; 16 const int major; 17 const int minor; 18 }; 19 20 static const struct ath79_soc_desc desc[] = { 21 {ATH79_SOC_AR7130, "7130", 22 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130}, 23 {ATH79_SOC_AR7141, "7141", 24 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141}, 25 {ATH79_SOC_AR7161, "7161", 26 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161}, 27 {ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0}, 28 {ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0}, 29 {ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0}, 30 {ATH79_SOC_AR9130, "9130", 31 REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130}, 32 {ATH79_SOC_AR9132, "9132", 33 REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132}, 34 {ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0}, 35 {ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0}, 36 {ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0}, 37 {ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0}, 38 {ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0}, 39 {ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0}, 40 {ATH79_SOC_QCA9533, "9533", 41 REV_ID_MAJOR_QCA9533_V2, 0}, 42 {ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0}, 43 {ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0}, 44 {ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0}, 45 {ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0}, 46 }; 47 48 int mach_cpu_init(void) 49 { 50 void __iomem *base; 51 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; 52 u32 id, major, minor = 0; 53 u32 rev = 0, ver = 1; 54 int i; 55 56 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, 57 MAP_NOCACHE); 58 59 id = readl(base + AR71XX_RESET_REG_REV_ID); 60 major = id & REV_ID_MAJOR_MASK; 61 switch (major) { 62 case REV_ID_MAJOR_AR71XX: 63 case REV_ID_MAJOR_AR913X: 64 minor = id & AR71XX_REV_ID_MINOR_MASK; 65 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 66 rev &= AR71XX_REV_ID_REVISION_MASK; 67 break; 68 69 case REV_ID_MAJOR_QCA9533_V2: 70 ver = 2; 71 /* drop through */ 72 73 case REV_ID_MAJOR_AR9341: 74 case REV_ID_MAJOR_AR9342: 75 case REV_ID_MAJOR_AR9344: 76 case REV_ID_MAJOR_QCA9533: 77 case REV_ID_MAJOR_QCA9556: 78 case REV_ID_MAJOR_QCA9558: 79 case REV_ID_MAJOR_TP9343: 80 case REV_ID_MAJOR_QCA9561: 81 rev = id & AR71XX_REV_ID_REVISION2_MASK; 82 break; 83 default: 84 rev = id & AR71XX_REV_ID_REVISION_MASK; 85 break; 86 } 87 88 for (i = 0; i < ARRAY_SIZE(desc); i++) { 89 if ((desc[i].major == major) && 90 (desc[i].minor == minor)) { 91 soc = desc[i].soc; 92 break; 93 } 94 } 95 96 gd->arch.id = id; 97 gd->arch.soc = soc; 98 gd->arch.rev = rev; 99 gd->arch.ver = ver; 100 return 0; 101 } 102 103 int print_cpuinfo(void) 104 { 105 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; 106 const char *chip = "????"; 107 u32 id, rev, ver; 108 int i; 109 110 for (i = 0; i < ARRAY_SIZE(desc); i++) { 111 if (desc[i].soc == gd->arch.soc) { 112 chip = desc[i].chip; 113 soc = desc[i].soc; 114 break; 115 } 116 } 117 118 id = gd->arch.id; 119 rev = gd->arch.rev; 120 ver = gd->arch.ver; 121 122 switch (soc) { 123 case ATH79_SOC_QCA9533: 124 case ATH79_SOC_QCA9556: 125 case ATH79_SOC_QCA9558: 126 case ATH79_SOC_QCA9561: 127 printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, 128 ver, rev); 129 break; 130 case ATH79_SOC_TP9343: 131 printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); 132 break; 133 case ATH79_SOC_UNKNOWN: 134 printf("ATH79: unknown SoC, id:0x%08x", id); 135 break; 136 default: 137 printf("Atheros AR%s rev %u\n", chip, rev); 138 } 139 140 return 0; 141 } 142