1 /* 2 * Copyright (C) 2016 Marek Vasut <marex@denx.de> 3 * 4 * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/addrspace.h> 12 #include <asm/types.h> 13 #include <mach/ar71xx_regs.h> 14 #include <mach/ath79.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 enum { 19 AR934X_SDRAM = 0, 20 AR934X_DDR1, 21 AR934X_DDR2, 22 }; 23 24 struct ar934x_mem_config { 25 u32 config1; 26 u32 config2; 27 u32 mode; 28 u32 extmode; 29 u32 tap; 30 }; 31 32 static const struct ar934x_mem_config ar934x_mem_config[] = { 33 [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f }, 34 [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 }, 35 [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 }, 36 }; 37 38 void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) 39 { 40 void __iomem *ddr_regs; 41 const struct ar934x_mem_config *memcfg; 42 int memtype; 43 u32 reg, cycle, ctl; 44 45 ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, 46 MAP_NOCACHE); 47 48 reg = ath79_get_bootstrap(); 49 if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */ 50 if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */ 51 memtype = AR934X_DDR1; 52 cycle = 0xffff; 53 } else { /* DDR 2 */ 54 memtype = AR934X_DDR2; 55 if (gd->arch.rev) { 56 ctl = BIT(6); /* Undocumented bit :-( */ 57 if (reg & BIT(3)) 58 cycle = 0xff; 59 else 60 cycle = 0xffff; 61 } else { 62 /* Force DDR2/x16 configuratio on old chips. */ 63 ctl = 0; 64 cycle = 0xffff; /* DDR2 16bit */ 65 } 66 67 writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG); 68 udelay(100); 69 70 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); 71 udelay(10); 72 73 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); 74 udelay(10); 75 76 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); 77 udelay(10); 78 } 79 } else { /* SDRAM */ 80 memtype = AR934X_SDRAM; 81 cycle = 0xffffffff; 82 83 writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF); 84 udelay(100); 85 86 /* Undocumented register */ 87 writel(0x13b, ddr_regs + 0x118); 88 udelay(100); 89 } 90 91 memcfg = &ar934x_mem_config[memtype]; 92 93 writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG); 94 udelay(100); 95 96 writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); 97 udelay(100); 98 99 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); 100 udelay(10); 101 102 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE); 103 mdelay(1); 104 105 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); 106 udelay(10); 107 108 if (memtype == AR934X_DDR2) { 109 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR); 110 udelay(100); 111 112 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); 113 udelay(10); 114 } 115 116 if (memtype != AR934X_SDRAM) 117 writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR); 118 119 udelay(100); 120 121 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); 122 udelay(10); 123 124 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); 125 udelay(10); 126 127 writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE); 128 udelay(100); 129 130 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); 131 udelay(10); 132 133 writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH); 134 udelay(100); 135 136 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); 137 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); 138 139 if (memtype != AR934X_SDRAM) { 140 if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) { 141 writel(memcfg->tap, 142 ddr_regs + AR934X_DDR_REG_TAP_CTRL2); 143 writel(memcfg->tap, 144 ddr_regs + AR934X_DDR_REG_TAP_CTRL3); 145 } 146 } 147 148 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); 149 udelay(100); 150 151 writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST); 152 udelay(100); 153 154 writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2); 155 udelay(100); 156 157 writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX); 158 udelay(100); 159 } 160 161 void ddr_tap_tuning(void) 162 { 163 } 164