1/* 2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 3 * Based on Atheros LSDK/QSDK and u-boot_mod project 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <config.h> 9#include <asm/asm.h> 10#include <asm/regdef.h> 11#include <asm/mipsregs.h> 12#include <asm/addrspace.h> 13#include <mach/ar71xx_regs.h> 14 15#define SET_BIT(val, bit) ((val) | (1 << (bit))) 16#define SET_PLL_PD(val) SET_BIT(val, 30) 17#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) 18#define PLL_BYPASS(val) SET_BIT(val, 2) 19 20#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ 21 (((0x3F & divint) << 10) | \ 22 ((0x1F & refdiv) << 16) | \ 23 ((0x1 & range) << 21) | \ 24 ((0x7 & outdiv) << 23) ) 25 26#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ 27 (((0x3 & (cpudiv - 1)) << 5) | \ 28 ((0x3 & (ddrdiv - 1)) << 10) | \ 29 ((0x3 & (ahbdiv - 1)) << 15) ) 30 31/* 32 * PLL_CPU_CONFIG_VAL 33 * 34 * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) 35 * After PLL configuration we need to clear this bit 36 * 37 * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) 38 * 39 * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) 40 * => 32 (0x20) VCOOUT = XTAL * DIV_INT 41 * bits 16..20 (5bit) REFDIV (Reference clock divider) 42 * => 1 (0x1) [Must start at values 1] 43 * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) 44 * => 0 (0x0) [Doesn't impact clock values] 45 * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) 46 * => 1 (0x1) [0 is illegal!] 47 * PLLOUT = VCOOUT * (1/2^OUTDIV) 48 */ 49/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ 50#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) 51/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ 52#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) 53 54/* 55 * PLL_CLK_CONTROL_VAL 56 * 57 * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) 58 * After PLL configuration we need to clear this bit 59 * 60 * Values written into CPU Clock Control Register CLOCK_CONTROL 61 * 62 * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. 63 * Software must enable the CPU PLL for normal and 64 * then set this bit to 0) 65 * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) 66 * CPU_CLK = PLLOUT / CPU_POST_DIV 67 * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) 68 * DDR_CLK = PLLOUT / DDR_POST_DIV 69 * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) 70 * AHB_CLK = PLLOUT / AHB_POST_DIV 71 * 72 */ 73#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) 74 75 .text 76 .set noreorder 77 78LEAF(lowlevel_init) 79 /* These three WLAN_RESET will avoid original issue */ 80 li t3, 0x03 811: 82 li t0, CKSEG1ADDR(AR71XX_RESET_BASE) 83 lw t1, AR933X_RESET_REG_RESET_MODULE(t0) 84 ori t1, t1, 0x0800 85 sw t1, AR933X_RESET_REG_RESET_MODULE(t0) 86 nop 87 lw t1, AR933X_RESET_REG_RESET_MODULE(t0) 88 li t2, 0xfffff7ff 89 and t1, t1, t2 90 sw t1, AR933X_RESET_REG_RESET_MODULE(t0) 91 nop 92 addi t3, t3, -1 93 bnez t3, 1b 94 nop 95 96 li t2, 0x20 972: 98 beqz t2, 1b 99 nop 100 addi t2, t2, -1 101 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0) 102 andi t1, t5, 0x10 103 bnez t1, 2b 104 nop 105 106 li t1, 0x02110E 107 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0) 108 nop 109 110 /* RTC Force Wake */ 111 li t0, CKSEG1ADDR(AR933X_RTC_BASE) 112 li t1, 0x03 113 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0) 114 nop 115 nop 116 117 /* RTC Reset */ 118 li t1, 0x00 119 sw t1, AR933X_RTC_REG_RESET(t0) 120 nop 121 nop 122 123 li t1, 0x01 124 sw t1, AR933X_RTC_REG_RESET(t0) 125 nop 126 nop 127 128 /* Wait for RTC in on state */ 1291: 130 lw t1, AR933X_RTC_REG_STATUS(t0) 131 andi t1, t1, 0x02 132 beqz t1, 1b 133 nop 134 135 /* Program ki/kd */ 136 li t0, CKSEG1ADDR(AR933X_SRIF_BASE) 137 andi t1, t5, 0x01 # t5 BOOT_STRAP 138 bnez t1, 1f 139 nop 140 li t1, 0x19e82f01 141 b 2f 142 nop 1431: 144 li t1, 0x18e82f01 1452: 146 sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0) 147 148 /* Program phase shift */ 149 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) 150 li t2, 0xc07fffff 151 and t1, t1, t2 152 li t2, 0x800000 153 or t1, t1, t2 154 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) 155 nop 156 157 /* in some cases, the SoC doesn't start with higher clock on AHB */ 158 li t0, CKSEG1ADDR(AR71XX_PLL_BASE) 159 li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) 160 sw t1, AR933X_PLL_CLK_CTRL_REG(t0) 161 nop 162 163 /* Set SETTLE_TIME in CPU PLL */ 164 andi t1, t5, 0x01 # t5 BOOT_STRAP 165 bnez t1, 1f 166 nop 167 li t1, 0x0352 168 b 2f 169 nop 1701: 171 li t1, 0x0550 1722: 173 sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0) 174 nop 175 176 /* Set nint, frac, refdiv, outdiv, range according to xtal */ 1770: 178 andi t1, t5, 0x01 # t5 BOOT_STRAP 179 bnez t1, 1f 180 nop 181 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) 182 b 2f 183 nop 1841: 185 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) 1862: 187 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) 188 nop 1891: 190 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) 191 li t2, 0x80000000 192 and t1, t1, t2 193 bnez t1, 1b 194 nop 195 196 /* Put frac bit19:10 configuration */ 197 li t1, 0x1003E8 198 sw t1, AR933X_PLL_DITHER_FRAC_REG(t0) 199 nop 200 201 /* Clear PLL power down bit in CPU PLL configuration */ 202 andi t1, t5, 0x01 # t5 BOOT_STRAP 203 bnez t1, 1f 204 nop 205 li t1, PLL_CPU_CONFIG_VAL_25M 206 b 2f 207 nop 2081: 209 li t1, PLL_CPU_CONFIG_VAL_40M 2102: 211 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) 212 nop 213 214 /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ 2151: 216 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) 217 li t2, 0x80000000 218 and t1, t1, t2 219 bnez t1, 1b 220 nop 221 222 /* Confirm DDR PLL lock */ 223 li t3, 100 224 li t4, 0 225 2262: 227 addi t4, t4, 1 228 bgt t4, t3, 0b 229 nop 230 231 li t3, 5 2323: 233 /* Clear do_meas */ 234 li t0, CKSEG1ADDR(AR933X_SRIF_BASE) 235 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) 236 li t2, 0xBFFFFFFF 237 and t1, t1, t2 238 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) 239 nop 240 241 li t2, 10 2421: 243 subu t2, t2, 1 244 bnez t2, 1b 245 nop 246 247 /* Set do_meas */ 248 li t2, 0x40000000 249 or t1, t1, t2 250 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) 251 nop 252 253 /* Check meas_done */ 2541: 255 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0) 256 andi t1, t1, 0x8 257 beqz t1, 1b 258 nop 259 260 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) 261 li t2, 0x007FFFF8 262 and t1, t1, t2 263 srl t1, t1, 3 264 li t2, 0x4000 265 bgt t1, t2, 2b 266 nop 267 addi t3, t3, -1 268 bnez t3, 3b 269 nop 270 271 /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ 272 li t0, CKSEG1ADDR(AR71XX_PLL_BASE) 273 li t1, PLL_CLK_CONTROL_VAL 274 sw t1, AR933X_PLL_CLK_CTRL_REG(t0) 275 nop 276 277 nop 278 jr ra 279 nop 280 END(lowlevel_init) 281