1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 1994 - 2002 by Ralf Baechle 4 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 5 * Copyright (C) 2002 Maciej W. Rozycki 6 */ 7 #ifndef _ASM_PGTABLE_BITS_H 8 #define _ASM_PGTABLE_BITS_H 9 10 11 /* 12 * Note that we shift the lower 32bits of each EntryLo[01] entry 13 * 6 bits to the left. That way we can convert the PFN into the 14 * physical address by a single 'and' operation and gain 6 additional 15 * bits for storing information which isn't present in a normal 16 * MIPS page table. 17 * 18 * Similar to the Alpha port, we need to keep track of the ref 19 * and mod bits in software. We have a software "yeah you can read 20 * from this page" bit, and a hardware one which actually lets the 21 * process read from the page. On the same token we have a software 22 * writable bit and the real hardware one which actually lets the 23 * process write to the page, this keeps a mod bit via the hardware 24 * dirty bit. 25 * 26 * Certain revisions of the R4000 and R5000 have a bug where if a 27 * certain sequence occurs in the last 3 instructions of an executable 28 * page, and the following page is not mapped, the cpu can do 29 * unpredictable things. The code (when it is written) to deal with 30 * this problem will be in the update_mmu_cache() code for the r4k. 31 */ 32 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 33 34 /* 35 * The following bits are implemented by the TLB hardware 36 */ 37 #define _PAGE_NO_EXEC_SHIFT 0 38 #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) 39 #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) 40 #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) 41 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 42 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 43 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 44 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 45 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 46 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 47 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 48 #define _CACHE_MASK (7 << _CACHE_SHIFT) 49 50 /* 51 * The following bits are implemented in software 52 */ 53 #define _PAGE_PRESENT_SHIFT (24) 54 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 55 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 56 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 57 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 58 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 59 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 60 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 61 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 62 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 63 64 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 65 66 /* 67 * Bits for extended EntryLo0/EntryLo1 registers 68 */ 69 #define _PFNX_MASK 0xffffff 70 71 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 72 73 /* 74 * The following bits are implemented in software 75 */ 76 #define _PAGE_PRESENT_SHIFT (0) 77 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 78 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 79 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 80 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 81 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 82 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 83 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 84 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 85 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 86 87 /* 88 * The following bits are implemented by the TLB hardware 89 */ 90 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4) 91 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 92 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 93 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 94 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 95 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 96 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1) 97 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) 98 #define _CACHE_MASK _CACHE_UNCACHED 99 100 #define _PFN_SHIFT PAGE_SHIFT 101 102 #else 103 /* 104 * Below are the "Normal" R4K cases 105 */ 106 107 /* 108 * The following bits are implemented in software 109 */ 110 #define _PAGE_PRESENT_SHIFT 0 111 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 112 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */ 113 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 114 #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) 115 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 116 #else 117 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 118 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 119 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 120 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 121 #endif 122 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 123 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 124 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 125 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 126 127 #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 128 /* Huge TLB page */ 129 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 130 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 131 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 132 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 133 #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ 134 135 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 136 /* XI - page cannot be executed */ 137 #ifdef _PAGE_SPLITTING_SHIFT 138 #define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 139 #else 140 #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 141 #endif 142 #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) 143 144 /* RI - page cannot be read */ 145 #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) 146 #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) 147 #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT 148 #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) 149 #endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */ 150 151 #if defined(_PAGE_NO_READ_SHIFT) 152 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 153 #elif defined(_PAGE_SPLITTING_SHIFT) 154 #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 155 #else 156 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 157 #endif 158 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 159 160 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 161 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 162 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 163 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 164 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 165 #define _CACHE_MASK (7 << _CACHE_SHIFT) 166 167 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 168 169 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 170 171 #ifndef _PAGE_NO_EXEC 172 #define _PAGE_NO_EXEC 0 173 #endif 174 #ifndef _PAGE_NO_READ 175 #define _PAGE_NO_READ 0 176 #endif 177 178 #define _PAGE_SILENT_READ _PAGE_VALID 179 #define _PAGE_SILENT_WRITE _PAGE_DIRTY 180 181 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 182 183 /* 184 * The final layouts of the PTE bits are: 185 * 186 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P 187 * 32-bit, R1 or earler: CCC D V G M A W R P 188 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P 189 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P 190 */ 191 192 193 #ifndef __ASSEMBLY__ 194 /* 195 * pte_to_entrylo converts a page table entry (PTE) into a Mips 196 * entrylo0/1 value. 197 */ 198 static inline uint64_t pte_to_entrylo(unsigned long pte_val) 199 { 200 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 201 if (cpu_has_rixi) { 202 int sa; 203 #ifdef CONFIG_32BIT 204 sa = 31 - _PAGE_NO_READ_SHIFT; 205 #else 206 sa = 63 - _PAGE_NO_READ_SHIFT; 207 #endif 208 /* 209 * C has no way to express that this is a DSRL 210 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily 211 * in the fast path this is done in assembly 212 */ 213 return (pte_val >> _PAGE_GLOBAL_SHIFT) | 214 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); 215 } 216 #endif 217 218 return pte_val >> _PAGE_GLOBAL_SHIFT; 219 } 220 #endif 221 222 /* 223 * Cache attributes 224 */ 225 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 226 227 #define _CACHE_CACHABLE_NONCOHERENT 0 228 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED 229 230 #elif defined(CONFIG_CPU_SB1) 231 232 /* No penalty for being coherent on the SB1, so just 233 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 234 235 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 236 237 #elif defined(CONFIG_CPU_LOONGSON3) 238 239 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ 240 241 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ 242 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ 243 244 #elif defined(CONFIG_MACH_INGENIC) 245 246 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 247 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) 248 249 #endif 250 251 #ifndef _CACHE_CACHABLE_NO_WA 252 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) 253 #endif 254 #ifndef _CACHE_CACHABLE_WA 255 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) 256 #endif 257 #ifndef _CACHE_UNCACHED 258 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) 259 #endif 260 #ifndef _CACHE_CACHABLE_NONCOHERENT 261 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) 262 #endif 263 #ifndef _CACHE_CACHABLE_CE 264 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) 265 #endif 266 #ifndef _CACHE_CACHABLE_COW 267 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) 268 #endif 269 #ifndef _CACHE_CACHABLE_CUW 270 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) 271 #endif 272 #ifndef _CACHE_UNCACHED_ACCELERATED 273 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 274 #endif 275 276 #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED) 277 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) 278 279 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ 280 _PFN_MASK | _CACHE_MASK) 281 282 #endif /* _ASM_PGTABLE_BITS_H */ 283