1 /* 2 * Copyright (C) 1994 - 2002 by Ralf Baechle 3 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 4 * Copyright (C) 2002 Maciej W. Rozycki 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 #ifndef _ASM_PGTABLE_BITS_H 9 #define _ASM_PGTABLE_BITS_H 10 11 12 /* 13 * Note that we shift the lower 32bits of each EntryLo[01] entry 14 * 6 bits to the left. That way we can convert the PFN into the 15 * physical address by a single 'and' operation and gain 6 additional 16 * bits for storing information which isn't present in a normal 17 * MIPS page table. 18 * 19 * Similar to the Alpha port, we need to keep track of the ref 20 * and mod bits in software. We have a software "yeah you can read 21 * from this page" bit, and a hardware one which actually lets the 22 * process read from the page. On the same token we have a software 23 * writable bit and the real hardware one which actually lets the 24 * process write to the page, this keeps a mod bit via the hardware 25 * dirty bit. 26 * 27 * Certain revisions of the R4000 and R5000 have a bug where if a 28 * certain sequence occurs in the last 3 instructions of an executable 29 * page, and the following page is not mapped, the cpu can do 30 * unpredictable things. The code (when it is written) to deal with 31 * this problem will be in the update_mmu_cache() code for the r4k. 32 */ 33 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 34 35 /* 36 * The following bits are implemented by the TLB hardware 37 */ 38 #define _PAGE_NO_EXEC_SHIFT 0 39 #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) 40 #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) 41 #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) 42 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 43 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 44 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 45 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 46 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 47 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 48 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 49 #define _CACHE_MASK (7 << _CACHE_SHIFT) 50 51 /* 52 * The following bits are implemented in software 53 */ 54 #define _PAGE_PRESENT_SHIFT (24) 55 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 56 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 57 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 58 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 59 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 60 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 61 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 62 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 63 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 64 65 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 66 67 /* 68 * Bits for extended EntryLo0/EntryLo1 registers 69 */ 70 #define _PFNX_MASK 0xffffff 71 72 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 73 74 /* 75 * The following bits are implemented in software 76 */ 77 #define _PAGE_PRESENT_SHIFT (0) 78 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 79 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 80 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 81 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 82 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 83 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 84 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 85 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 86 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 87 88 /* 89 * The following bits are implemented by the TLB hardware 90 */ 91 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4) 92 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 93 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 94 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 95 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 96 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 97 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1) 98 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) 99 #define _CACHE_MASK _CACHE_UNCACHED 100 101 #define _PFN_SHIFT PAGE_SHIFT 102 103 #else 104 /* 105 * Below are the "Normal" R4K cases 106 */ 107 108 /* 109 * The following bits are implemented in software 110 */ 111 #define _PAGE_PRESENT_SHIFT 0 112 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 113 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */ 114 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 115 #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) 116 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 117 #else 118 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 119 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 120 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 121 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 122 #endif 123 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 124 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 125 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 126 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 127 128 #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 129 /* Huge TLB page */ 130 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 131 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 132 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 133 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 134 #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ 135 136 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 137 /* XI - page cannot be executed */ 138 #ifdef _PAGE_SPLITTING_SHIFT 139 #define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 140 #else 141 #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 142 #endif 143 #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) 144 145 /* RI - page cannot be read */ 146 #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) 147 #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) 148 #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT 149 #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) 150 #endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */ 151 152 #if defined(_PAGE_NO_READ_SHIFT) 153 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 154 #elif defined(_PAGE_SPLITTING_SHIFT) 155 #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 156 #else 157 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 158 #endif 159 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 160 161 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 162 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 163 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 164 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 165 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 166 #define _CACHE_MASK (7 << _CACHE_SHIFT) 167 168 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 169 170 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 171 172 #ifndef _PAGE_NO_EXEC 173 #define _PAGE_NO_EXEC 0 174 #endif 175 #ifndef _PAGE_NO_READ 176 #define _PAGE_NO_READ 0 177 #endif 178 179 #define _PAGE_SILENT_READ _PAGE_VALID 180 #define _PAGE_SILENT_WRITE _PAGE_DIRTY 181 182 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 183 184 /* 185 * The final layouts of the PTE bits are: 186 * 187 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P 188 * 32-bit, R1 or earler: CCC D V G M A W R P 189 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P 190 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P 191 */ 192 193 194 #ifndef __ASSEMBLY__ 195 /* 196 * pte_to_entrylo converts a page table entry (PTE) into a Mips 197 * entrylo0/1 value. 198 */ 199 static inline uint64_t pte_to_entrylo(unsigned long pte_val) 200 { 201 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 202 if (cpu_has_rixi) { 203 int sa; 204 #ifdef CONFIG_32BIT 205 sa = 31 - _PAGE_NO_READ_SHIFT; 206 #else 207 sa = 63 - _PAGE_NO_READ_SHIFT; 208 #endif 209 /* 210 * C has no way to express that this is a DSRL 211 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily 212 * in the fast path this is done in assembly 213 */ 214 return (pte_val >> _PAGE_GLOBAL_SHIFT) | 215 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); 216 } 217 #endif 218 219 return pte_val >> _PAGE_GLOBAL_SHIFT; 220 } 221 #endif 222 223 /* 224 * Cache attributes 225 */ 226 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 227 228 #define _CACHE_CACHABLE_NONCOHERENT 0 229 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED 230 231 #elif defined(CONFIG_CPU_SB1) 232 233 /* No penalty for being coherent on the SB1, so just 234 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 235 236 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 237 238 #elif defined(CONFIG_CPU_LOONGSON3) 239 240 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ 241 242 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ 243 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ 244 245 #elif defined(CONFIG_MACH_INGENIC) 246 247 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 248 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) 249 250 #endif 251 252 #ifndef _CACHE_CACHABLE_NO_WA 253 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) 254 #endif 255 #ifndef _CACHE_CACHABLE_WA 256 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) 257 #endif 258 #ifndef _CACHE_UNCACHED 259 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) 260 #endif 261 #ifndef _CACHE_CACHABLE_NONCOHERENT 262 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) 263 #endif 264 #ifndef _CACHE_CACHABLE_CE 265 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) 266 #endif 267 #ifndef _CACHE_CACHABLE_COW 268 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) 269 #endif 270 #ifndef _CACHE_CACHABLE_CUW 271 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) 272 #endif 273 #ifndef _CACHE_UNCACHED_ACCELERATED 274 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 275 #endif 276 277 #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED) 278 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) 279 280 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ 281 _PFN_MASK | _CACHE_MASK) 282 283 #endif /* _ASM_PGTABLE_BITS_H */ 284