xref: /openbmc/u-boot/arch/mips/include/asm/mipsregs.h (revision ef64e782)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
4  * Copyright (C) 2000 Silicon Graphics, Inc.
5  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
6  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
7  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
8  * Copyright (C) 2003, 2004  Maciej W. Rozycki
9  */
10 #ifndef _ASM_MIPSREGS_H
11 #define _ASM_MIPSREGS_H
12 
13 /*
14  * The following macros are especially useful for __asm__
15  * inline assembler.
16  */
17 #ifndef __STR
18 #define __STR(x) #x
19 #endif
20 #ifndef STR
21 #define STR(x) __STR(x)
22 #endif
23 
24 /*
25  *  Configure language
26  */
27 #ifdef __ASSEMBLY__
28 #define _ULCAST_
29 #else
30 #define _ULCAST_ (unsigned long)
31 #endif
32 
33 /*
34  * Coprocessor 0 register names
35  */
36 #define CP0_INDEX $0
37 #define CP0_RANDOM $1
38 #define CP0_ENTRYLO0 $2
39 #define CP0_ENTRYLO1 $3
40 #define CP0_CONF $3
41 #define CP0_GLOBALNUMBER $3, 1
42 #define CP0_CONTEXT $4
43 #define CP0_PAGEMASK $5
44 #define CP0_WIRED $6
45 #define CP0_INFO $7
46 #define CP0_HWRENA $7, 0
47 #define CP0_BADVADDR $8
48 #define CP0_BADINSTR $8, 1
49 #define CP0_COUNT $9
50 #define CP0_ENTRYHI $10
51 #define CP0_COMPARE $11
52 #define CP0_STATUS $12
53 #define CP0_CAUSE $13
54 #define CP0_EPC $14
55 #define CP0_PRID $15
56 #define CP0_EBASE $15, 1
57 #define CP0_CMGCRBASE $15, 3
58 #define CP0_CONFIG $16
59 #define CP0_CONFIG3 $16, 3
60 #define CP0_CONFIG5 $16, 5
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
76 
77 /*
78  * R4640/R4650 cp0 register names.  These registers are listed
79  * here only for completeness; without MMU these CPUs are not useable
80  * by Linux.  A future ELKS port might take make Linux run on them
81  * though ...
82  */
83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3
87 #define CP0_CALG $17
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
90 
91 /*
92  * Coprocessor 0 Set 1 register names
93  */
94 #define CP0_S1_DERRADDR0  $26
95 #define CP0_S1_DERRADDR1  $27
96 #define CP0_S1_INTCONTROL $20
97 
98 /*
99  * Coprocessor 0 Set 2 register names
100  */
101 #define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
102 
103 /*
104  * Coprocessor 0 Set 3 register names
105  */
106 #define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
107 
108 /*
109  *  TX39 Series
110  */
111 #define CP0_TX39_CACHE	$7
112 
113 
114 /* Generic EntryLo bit definitions */
115 #define ENTRYLO_G		(_ULCAST_(1) << 0)
116 #define ENTRYLO_V		(_ULCAST_(1) << 1)
117 #define ENTRYLO_D		(_ULCAST_(1) << 2)
118 #define ENTRYLO_C_SHIFT		3
119 #define ENTRYLO_C		(_ULCAST_(7) << ENTRYLO_C_SHIFT)
120 
121 /* R3000 EntryLo bit definitions */
122 #define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
123 #define R3K_ENTRYLO_V		(_ULCAST_(1) << 9)
124 #define R3K_ENTRYLO_D		(_ULCAST_(1) << 10)
125 #define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)
126 
127 /* MIPS32/64 EntryLo bit definitions */
128 #define MIPS_ENTRYLO_PFN_SHIFT	6
129 #define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
130 #define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
131 
132 /*
133  * Values for PageMask register
134  */
135 #ifdef CONFIG_CPU_VR41XX
136 
137 /* Why doesn't stupidity hurt ... */
138 
139 #define PM_1K		0x00000000
140 #define PM_4K		0x00001800
141 #define PM_16K		0x00007800
142 #define PM_64K		0x0001f800
143 #define PM_256K		0x0007f800
144 
145 #else
146 
147 #define PM_4K		0x00000000
148 #define PM_8K		0x00002000
149 #define PM_16K		0x00006000
150 #define PM_32K		0x0000e000
151 #define PM_64K		0x0001e000
152 #define PM_128K		0x0003e000
153 #define PM_256K		0x0007e000
154 #define PM_512K		0x000fe000
155 #define PM_1M		0x001fe000
156 #define PM_2M		0x003fe000
157 #define PM_4M		0x007fe000
158 #define PM_8M		0x00ffe000
159 #define PM_16M		0x01ffe000
160 #define PM_32M		0x03ffe000
161 #define PM_64M		0x07ffe000
162 #define PM_256M		0x1fffe000
163 #define PM_1G		0x7fffe000
164 
165 #endif
166 
167 /*
168  * Values used for computation of new tlb entries
169  */
170 #define PL_4K		12
171 #define PL_16K		14
172 #define PL_64K		16
173 #define PL_256K		18
174 #define PL_1M		20
175 #define PL_4M		22
176 #define PL_16M		24
177 #define PL_64M		26
178 #define PL_256M		28
179 
180 /*
181  * PageGrain bits
182  */
183 #define PG_RIE		(_ULCAST_(1) <<	 31)
184 #define PG_XIE		(_ULCAST_(1) <<	 30)
185 #define PG_ELPA		(_ULCAST_(1) <<	 29)
186 #define PG_ESP		(_ULCAST_(1) <<	 28)
187 #define PG_IEC		(_ULCAST_(1) <<  27)
188 
189 /* MIPS32/64 EntryHI bit definitions */
190 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
191 
192 /*
193  * R4x00 interrupt enable / cause bits
194  */
195 #define IE_SW0		(_ULCAST_(1) <<	 8)
196 #define IE_SW1		(_ULCAST_(1) <<	 9)
197 #define IE_IRQ0		(_ULCAST_(1) << 10)
198 #define IE_IRQ1		(_ULCAST_(1) << 11)
199 #define IE_IRQ2		(_ULCAST_(1) << 12)
200 #define IE_IRQ3		(_ULCAST_(1) << 13)
201 #define IE_IRQ4		(_ULCAST_(1) << 14)
202 #define IE_IRQ5		(_ULCAST_(1) << 15)
203 
204 /*
205  * R4x00 interrupt cause bits
206  */
207 #define C_SW0		(_ULCAST_(1) <<	 8)
208 #define C_SW1		(_ULCAST_(1) <<	 9)
209 #define C_IRQ0		(_ULCAST_(1) << 10)
210 #define C_IRQ1		(_ULCAST_(1) << 11)
211 #define C_IRQ2		(_ULCAST_(1) << 12)
212 #define C_IRQ3		(_ULCAST_(1) << 13)
213 #define C_IRQ4		(_ULCAST_(1) << 14)
214 #define C_IRQ5		(_ULCAST_(1) << 15)
215 
216 /*
217  * Bitfields in the R4xx0 cp0 status register
218  */
219 #define ST0_IE			0x00000001
220 #define ST0_EXL			0x00000002
221 #define ST0_ERL			0x00000004
222 #define ST0_KSU			0x00000018
223 #  define KSU_USER		0x00000010
224 #  define KSU_SUPERVISOR	0x00000008
225 #  define KSU_KERNEL		0x00000000
226 #define ST0_UX			0x00000020
227 #define ST0_SX			0x00000040
228 #define ST0_KX			0x00000080
229 #define ST0_DE			0x00010000
230 #define ST0_CE			0x00020000
231 
232 /*
233  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
234  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
235  * processors.
236  */
237 #define ST0_CO			0x08000000
238 
239 /*
240  * Bitfields in the R[23]000 cp0 status register.
241  */
242 #define ST0_IEC			0x00000001
243 #define ST0_KUC			0x00000002
244 #define ST0_IEP			0x00000004
245 #define ST0_KUP			0x00000008
246 #define ST0_IEO			0x00000010
247 #define ST0_KUO			0x00000020
248 /* bits 6 & 7 are reserved on R[23]000 */
249 #define ST0_ISC			0x00010000
250 #define ST0_SWC			0x00020000
251 #define ST0_CM			0x00080000
252 
253 /*
254  * Bits specific to the R4640/R4650
255  */
256 #define ST0_UM			(_ULCAST_(1) <<	 4)
257 #define ST0_IL			(_ULCAST_(1) << 23)
258 #define ST0_DL			(_ULCAST_(1) << 24)
259 
260 /*
261  * Enable the MIPS MDMX and DSP ASEs
262  */
263 #define ST0_MX			0x01000000
264 
265 /*
266  * Status register bits available in all MIPS CPUs.
267  */
268 #define ST0_IM			0x0000ff00
269 #define	 STATUSB_IP0		8
270 #define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
271 #define	 STATUSB_IP1		9
272 #define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
273 #define	 STATUSB_IP2		10
274 #define	 STATUSF_IP2		(_ULCAST_(1) << 10)
275 #define	 STATUSB_IP3		11
276 #define	 STATUSF_IP3		(_ULCAST_(1) << 11)
277 #define	 STATUSB_IP4		12
278 #define	 STATUSF_IP4		(_ULCAST_(1) << 12)
279 #define	 STATUSB_IP5		13
280 #define	 STATUSF_IP5		(_ULCAST_(1) << 13)
281 #define	 STATUSB_IP6		14
282 #define	 STATUSF_IP6		(_ULCAST_(1) << 14)
283 #define	 STATUSB_IP7		15
284 #define	 STATUSF_IP7		(_ULCAST_(1) << 15)
285 #define	 STATUSB_IP8		0
286 #define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
287 #define	 STATUSB_IP9		1
288 #define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
289 #define	 STATUSB_IP10		2
290 #define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
291 #define	 STATUSB_IP11		3
292 #define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
293 #define	 STATUSB_IP12		4
294 #define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
295 #define	 STATUSB_IP13		5
296 #define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
297 #define	 STATUSB_IP14		6
298 #define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
299 #define	 STATUSB_IP15		7
300 #define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
301 #define ST0_IMPL		(_ULCAST_(3) <<	 16)
302 #define ST0_CH			0x00040000
303 #define ST0_NMI			0x00080000
304 #define ST0_SR			0x00100000
305 #define ST0_TS			0x00200000
306 #define ST0_BEV			0x00400000
307 #define ST0_RE			0x02000000
308 #define ST0_FR			0x04000000
309 #define ST0_CU			0xf0000000
310 #define ST0_CU0			0x10000000
311 #define ST0_CU1			0x20000000
312 #define ST0_CU2			0x40000000
313 #define ST0_CU3			0x80000000
314 #define ST0_XX			0x80000000	/* MIPS IV naming */
315 
316 /*
317  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
318  */
319 #define INTCTLB_IPFDC		23
320 #define INTCTLF_IPFDC		(_ULCAST_(7) << INTCTLB_IPFDC)
321 #define INTCTLB_IPPCI		26
322 #define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
323 #define INTCTLB_IPTI		29
324 #define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)
325 
326 /*
327  * Bitfields and bit numbers in the coprocessor 0 cause register.
328  *
329  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
330  */
331 #define CAUSEB_EXCCODE		2
332 #define CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
333 #define CAUSEB_IP		8
334 #define CAUSEF_IP		(_ULCAST_(255) <<  8)
335 #define	 CAUSEB_IP0		8
336 #define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
337 #define	 CAUSEB_IP1		9
338 #define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
339 #define	 CAUSEB_IP2		10
340 #define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
341 #define	 CAUSEB_IP3		11
342 #define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
343 #define	 CAUSEB_IP4		12
344 #define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
345 #define	 CAUSEB_IP5		13
346 #define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
347 #define	 CAUSEB_IP6		14
348 #define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
349 #define	 CAUSEB_IP7		15
350 #define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
351 #define CAUSEB_FDCI		21
352 #define CAUSEF_FDCI		(_ULCAST_(1)   << 21)
353 #define CAUSEB_IV		23
354 #define CAUSEF_IV		(_ULCAST_(1)   << 23)
355 #define CAUSEB_PCI		26
356 #define CAUSEF_PCI		(_ULCAST_(1)   << 26)
357 #define CAUSEB_CE		28
358 #define CAUSEF_CE		(_ULCAST_(3)   << 28)
359 #define CAUSEB_TI		30
360 #define CAUSEF_TI		(_ULCAST_(1)   << 30)
361 #define CAUSEB_BD		31
362 #define CAUSEF_BD		(_ULCAST_(1)   << 31)
363 
364 /*
365  * Bits in the coprocessor 0 EBase register.
366  */
367 #define EBASE_CPUNUM		0x3ff
368 
369 /*
370  * Bits in the coprocessor 0 config register.
371  */
372 /* Generic bits.  */
373 #define CONF_CM_CACHABLE_NO_WA		0
374 #define CONF_CM_CACHABLE_WA		1
375 #define CONF_CM_UNCACHED		2
376 #define CONF_CM_CACHABLE_NONCOHERENT	3
377 #define CONF_CM_CACHABLE_CE		4
378 #define CONF_CM_CACHABLE_COW		5
379 #define CONF_CM_CACHABLE_CUW		6
380 #define CONF_CM_CACHABLE_ACCELERATED	7
381 #define CONF_CM_CMASK			7
382 #define CONF_BE			(_ULCAST_(1) << 15)
383 
384 /* Bits common to various processors.  */
385 #define CONF_CU			(_ULCAST_(1) <<	 3)
386 #define CONF_DB			(_ULCAST_(1) <<	 4)
387 #define CONF_IB			(_ULCAST_(1) <<	 5)
388 #define CONF_DC			(_ULCAST_(7) <<	 6)
389 #define CONF_IC			(_ULCAST_(7) <<	 9)
390 #define CONF_EB			(_ULCAST_(1) << 13)
391 #define CONF_EM			(_ULCAST_(1) << 14)
392 #define CONF_SM			(_ULCAST_(1) << 16)
393 #define CONF_SC			(_ULCAST_(1) << 17)
394 #define CONF_EW			(_ULCAST_(3) << 18)
395 #define CONF_EP			(_ULCAST_(15) << 24)
396 #define CONF_EC			(_ULCAST_(7) << 28)
397 #define CONF_CM			(_ULCAST_(1) << 31)
398 
399 /* Bits specific to the R4xx0.	*/
400 #define R4K_CONF_SW		(_ULCAST_(1) << 20)
401 #define R4K_CONF_SS		(_ULCAST_(1) << 21)
402 #define R4K_CONF_SB		(_ULCAST_(3) << 22)
403 
404 /* Bits specific to the R5000.	*/
405 #define R5K_CONF_SE		(_ULCAST_(1) << 12)
406 #define R5K_CONF_SS		(_ULCAST_(3) << 20)
407 
408 /* Bits specific to the RM7000.	 */
409 #define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
410 #define RM7K_CONF_TE		(_ULCAST_(1) << 12)
411 #define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
412 #define RM7K_CONF_TC		(_ULCAST_(1) << 17)
413 #define RM7K_CONF_SI		(_ULCAST_(3) << 20)
414 #define RM7K_CONF_SC		(_ULCAST_(1) << 31)
415 
416 /* Bits specific to the R10000.	 */
417 #define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
418 #define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
419 #define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
420 #define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
421 #define R10K_CONF_EC		(_ULCAST_(15) << 9)
422 #define R10K_CONF_SB		(_ULCAST_(1) << 13)
423 #define R10K_CONF_SK		(_ULCAST_(1) << 14)
424 #define R10K_CONF_SS		(_ULCAST_(7) << 16)
425 #define R10K_CONF_SC		(_ULCAST_(7) << 19)
426 #define R10K_CONF_DC		(_ULCAST_(7) << 26)
427 #define R10K_CONF_IC		(_ULCAST_(7) << 29)
428 
429 /* Bits specific to the VR41xx.	 */
430 #define VR41_CONF_CS		(_ULCAST_(1) << 12)
431 #define VR41_CONF_P4K		(_ULCAST_(1) << 13)
432 #define VR41_CONF_BP		(_ULCAST_(1) << 16)
433 #define VR41_CONF_M16		(_ULCAST_(1) << 20)
434 #define VR41_CONF_AD		(_ULCAST_(1) << 23)
435 
436 /* Bits specific to the R30xx.	*/
437 #define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
438 #define R30XX_CONF_REV		(_ULCAST_(1) << 22)
439 #define R30XX_CONF_AC		(_ULCAST_(1) << 23)
440 #define R30XX_CONF_RF		(_ULCAST_(1) << 24)
441 #define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
442 #define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
443 #define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
444 #define R30XX_CONF_SB		(_ULCAST_(1) << 30)
445 #define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
446 
447 /* Bits specific to the TX49.  */
448 #define TX49_CONF_DC		(_ULCAST_(1) << 16)
449 #define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
450 #define TX49_CONF_HALT		(_ULCAST_(1) << 18)
451 #define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
452 
453 /* Bits specific to the MIPS32/64 PRA.	*/
454 #define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
455 #define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)
456 #define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
457 #define MIPS_CONF_AR		(_ULCAST_(7) << 10)
458 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
459 #define MIPS_CONF_IMPL		(_ULCAST_(0x1ff) << 16)
460 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
461 
462 /*
463  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
464  */
465 #define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
466 #define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
467 #define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
468 #define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
469 #define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
470 #define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
471 #define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
472 #define MIPS_CONF1_DA_SHF	7
473 #define MIPS_CONF1_DA_SZ	3
474 #define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
475 #define MIPS_CONF1_DL_SHF	10
476 #define MIPS_CONF1_DL_SZ	3
477 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
478 #define MIPS_CONF1_DS_SHF	13
479 #define MIPS_CONF1_DS_SZ	3
480 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
481 #define MIPS_CONF1_IA_SHF	16
482 #define MIPS_CONF1_IA_SZ	3
483 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
484 #define MIPS_CONF1_IL_SHF	19
485 #define MIPS_CONF1_IL_SZ	3
486 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
487 #define MIPS_CONF1_IS_SHF	22
488 #define MIPS_CONF1_IS_SZ	3
489 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
490 #define MIPS_CONF1_TLBS_SHIFT   (25)
491 #define MIPS_CONF1_TLBS_SIZE    (6)
492 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
493 
494 #define MIPS_CONF2_SA_SHF	0
495 #define MIPS_CONF2_SA		(_ULCAST_(15) << 0)
496 #define MIPS_CONF2_SL_SHF	4
497 #define MIPS_CONF2_SL		(_ULCAST_(15) << 4)
498 #define MIPS_CONF2_SS_SHF	8
499 #define MIPS_CONF2_SS		(_ULCAST_(15) << 8)
500 #define MIPS_CONF2_L2B		(_ULCAST_(1) << 12)
501 #define MIPS_CONF2_SU		(_ULCAST_(15) << 12)
502 #define MIPS_CONF2_TA		(_ULCAST_(15) << 16)
503 #define MIPS_CONF2_TL		(_ULCAST_(15) << 20)
504 #define MIPS_CONF2_TS		(_ULCAST_(15) << 24)
505 #define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
506 
507 #define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
508 #define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
509 #define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
510 #define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
511 #define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
512 #define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
513 #define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
514 #define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
515 #define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
516 #define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
517 #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
518 #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
519 #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
520 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
521 #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
522 #define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
523 #define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
524 #define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
525 #define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
526 #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
527 #define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
528 #define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
529 #define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
530 #define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
531 #define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
532 #define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
533 #define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
534 
535 #define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
536 #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
537 #define MIPS_CONF4_FTLBSETS_SHIFT	(0)
538 #define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
539 #define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
540 #define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
541 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
542 /* bits 10:8 in FTLB-only configurations */
543 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
544 /* bits 12:8 in VTLB-FTLB only configurations */
545 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
546 #define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
547 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
548 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
549 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
550 #define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << 16)
551 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
552 #define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
553 #define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
554 #define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
555 #define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
556 
557 #define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
558 #define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
559 #define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
560 #define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)
561 #define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)
562 #define MIPS_CONF5_VP		(_ULCAST_(1) << 7)
563 #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
564 #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
565 #define MIPS_CONF5_L2C		(_ULCAST_(1) << 10)
566 #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
567 #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
568 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
569 #define MIPS_CONF5_K		(_ULCAST_(1) << 30)
570 
571 #define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
572 /* proAptiv FTLB on/off bit */
573 #define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
574 /* FTLB probability bits */
575 #define MIPS_CONF6_FTLBP_SHIFT	(16)
576 
577 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
578 
579 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
580 
581 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
582 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
583 /* FTLB probability bits for R6 */
584 #define MIPS_CONF7_FTLBP_SHIFT	(18)
585 
586 /* MAAR bit definitions */
587 #define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
588 #define MIPS_MAAR_ADDR_SHIFT	12
589 #define MIPS_MAAR_S		(_ULCAST_(1) << 1)
590 #define MIPS_MAAR_V		(_ULCAST_(1) << 0)
591 
592 /* CMGCRBase bit definitions */
593 #define MIPS_CMGCRB_BASE	11
594 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
595 
596 /*
597  * Bits in the MIPS32 Memory Segmentation registers.
598  */
599 #define MIPS_SEGCFG_PA_SHIFT	9
600 #define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
601 #define MIPS_SEGCFG_AM_SHIFT	4
602 #define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
603 #define MIPS_SEGCFG_EU_SHIFT	3
604 #define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
605 #define MIPS_SEGCFG_C_SHIFT	0
606 #define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
607 
608 #define MIPS_SEGCFG_UUSK	_ULCAST_(7)
609 #define MIPS_SEGCFG_USK		_ULCAST_(5)
610 #define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
611 #define MIPS_SEGCFG_MUSK	_ULCAST_(3)
612 #define MIPS_SEGCFG_MSK		_ULCAST_(2)
613 #define MIPS_SEGCFG_MK		_ULCAST_(1)
614 #define MIPS_SEGCFG_UK		_ULCAST_(0)
615 
616 #define MIPS_PWFIELD_GDI_SHIFT	24
617 #define MIPS_PWFIELD_GDI_MASK	0x3f000000
618 #define MIPS_PWFIELD_UDI_SHIFT	18
619 #define MIPS_PWFIELD_UDI_MASK	0x00fc0000
620 #define MIPS_PWFIELD_MDI_SHIFT	12
621 #define MIPS_PWFIELD_MDI_MASK	0x0003f000
622 #define MIPS_PWFIELD_PTI_SHIFT	6
623 #define MIPS_PWFIELD_PTI_MASK	0x00000fc0
624 #define MIPS_PWFIELD_PTEI_SHIFT	0
625 #define MIPS_PWFIELD_PTEI_MASK	0x0000003f
626 
627 #define MIPS_PWSIZE_GDW_SHIFT	24
628 #define MIPS_PWSIZE_GDW_MASK	0x3f000000
629 #define MIPS_PWSIZE_UDW_SHIFT	18
630 #define MIPS_PWSIZE_UDW_MASK	0x00fc0000
631 #define MIPS_PWSIZE_MDW_SHIFT	12
632 #define MIPS_PWSIZE_MDW_MASK	0x0003f000
633 #define MIPS_PWSIZE_PTW_SHIFT	6
634 #define MIPS_PWSIZE_PTW_MASK	0x00000fc0
635 #define MIPS_PWSIZE_PTEW_SHIFT	0
636 #define MIPS_PWSIZE_PTEW_MASK	0x0000003f
637 
638 #define MIPS_PWCTL_PWEN_SHIFT	31
639 #define MIPS_PWCTL_PWEN_MASK	0x80000000
640 #define MIPS_PWCTL_DPH_SHIFT	7
641 #define MIPS_PWCTL_DPH_MASK	0x00000080
642 #define MIPS_PWCTL_HUGEPG_SHIFT	6
643 #define MIPS_PWCTL_HUGEPG_MASK	0x00000060
644 #define MIPS_PWCTL_PSN_SHIFT	0
645 #define MIPS_PWCTL_PSN_MASK	0x0000003f
646 
647 /* CDMMBase register bit definitions */
648 #define MIPS_CDMMBASE_SIZE_SHIFT 0
649 #define MIPS_CDMMBASE_SIZE	(_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
650 #define MIPS_CDMMBASE_CI	(_ULCAST_(1) << 9)
651 #define MIPS_CDMMBASE_EN	(_ULCAST_(1) << 10)
652 #define MIPS_CDMMBASE_ADDR_SHIFT 11
653 #define MIPS_CDMMBASE_ADDR_START 15
654 
655 /*
656  * Bitfields in the TX39 family CP0 Configuration Register 3
657  */
658 #define TX39_CONF_ICS_SHIFT	19
659 #define TX39_CONF_ICS_MASK	0x00380000
660 #define TX39_CONF_ICS_1KB	0x00000000
661 #define TX39_CONF_ICS_2KB	0x00080000
662 #define TX39_CONF_ICS_4KB	0x00100000
663 #define TX39_CONF_ICS_8KB	0x00180000
664 #define TX39_CONF_ICS_16KB	0x00200000
665 
666 #define TX39_CONF_DCS_SHIFT	16
667 #define TX39_CONF_DCS_MASK	0x00070000
668 #define TX39_CONF_DCS_1KB	0x00000000
669 #define TX39_CONF_DCS_2KB	0x00010000
670 #define TX39_CONF_DCS_4KB	0x00020000
671 #define TX39_CONF_DCS_8KB	0x00030000
672 #define TX39_CONF_DCS_16KB	0x00040000
673 
674 #define TX39_CONF_CWFON		0x00004000
675 #define TX39_CONF_WBON		0x00002000
676 #define TX39_CONF_RF_SHIFT	10
677 #define TX39_CONF_RF_MASK	0x00000c00
678 #define TX39_CONF_DOZE		0x00000200
679 #define TX39_CONF_HALT		0x00000100
680 #define TX39_CONF_LOCK		0x00000080
681 #define TX39_CONF_ICE		0x00000020
682 #define TX39_CONF_DCE		0x00000010
683 #define TX39_CONF_IRSIZE_SHIFT	2
684 #define TX39_CONF_IRSIZE_MASK	0x0000000c
685 #define TX39_CONF_DRSIZE_SHIFT	0
686 #define TX39_CONF_DRSIZE_MASK	0x00000003
687 
688 /*
689  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
690  */
691 /* Disable Branch Target Address Cache */
692 #define R10K_DIAG_D_BTAC	(_ULCAST_(1) << 27)
693 /* Enable Branch Prediction Global History */
694 #define R10K_DIAG_E_GHIST	(_ULCAST_(1) << 26)
695 /* Disable Branch Return Cache */
696 #define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
697 
698 /*
699  * Coprocessor 1 (FPU) register names
700  */
701 #define CP1_REVISION	$0
702 #define CP1_UFR		$1
703 #define CP1_UNFR	$4
704 #define CP1_FCCR	$25
705 #define CP1_FEXR	$26
706 #define CP1_FENR	$28
707 #define CP1_STATUS	$31
708 
709 
710 /*
711  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
712  */
713 #define MIPS_FPIR_S		(_ULCAST_(1) << 16)
714 #define MIPS_FPIR_D		(_ULCAST_(1) << 17)
715 #define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
716 #define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
717 #define MIPS_FPIR_W		(_ULCAST_(1) << 20)
718 #define MIPS_FPIR_L		(_ULCAST_(1) << 21)
719 #define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
720 #define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
721 #define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
722 #define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
723 
724 /*
725  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
726  */
727 #define MIPS_FCCR_CONDX_S	0
728 #define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
729 #define MIPS_FCCR_COND0_S	0
730 #define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
731 #define MIPS_FCCR_COND1_S	1
732 #define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
733 #define MIPS_FCCR_COND2_S	2
734 #define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
735 #define MIPS_FCCR_COND3_S	3
736 #define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
737 #define MIPS_FCCR_COND4_S	4
738 #define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
739 #define MIPS_FCCR_COND5_S	5
740 #define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
741 #define MIPS_FCCR_COND6_S	6
742 #define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
743 #define MIPS_FCCR_COND7_S	7
744 #define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
745 
746 /*
747  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
748  */
749 #define MIPS_FENR_FS_S		2
750 #define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
751 
752 /*
753  * FPU Status Register Values
754  */
755 #define FPU_CSR_COND_S	23					/* $fcc0 */
756 #define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
757 
758 #define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
759 #define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
760 
761 #define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
762 #define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
763 #define FPU_CSR_COND1_S	25					/* $fcc1 */
764 #define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
765 #define FPU_CSR_COND2_S	26					/* $fcc2 */
766 #define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
767 #define FPU_CSR_COND3_S	27					/* $fcc3 */
768 #define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
769 #define FPU_CSR_COND4_S	28					/* $fcc4 */
770 #define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
771 #define FPU_CSR_COND5_S	29					/* $fcc5 */
772 #define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
773 #define FPU_CSR_COND6_S	30					/* $fcc6 */
774 #define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
775 #define FPU_CSR_COND7_S	31					/* $fcc7 */
776 #define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
777 
778 /*
779  * Bits 22:20 of the FPU Status Register will be read as 0,
780  * and should be written as zero.
781  */
782 #define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
783 
784 #define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
785 #define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
786 
787 /*
788  * X the exception cause indicator
789  * E the exception enable
790  * S the sticky/flag bit
791 */
792 #define FPU_CSR_ALL_X	0x0003f000
793 #define FPU_CSR_UNI_X	0x00020000
794 #define FPU_CSR_INV_X	0x00010000
795 #define FPU_CSR_DIV_X	0x00008000
796 #define FPU_CSR_OVF_X	0x00004000
797 #define FPU_CSR_UDF_X	0x00002000
798 #define FPU_CSR_INE_X	0x00001000
799 
800 #define FPU_CSR_ALL_E	0x00000f80
801 #define FPU_CSR_INV_E	0x00000800
802 #define FPU_CSR_DIV_E	0x00000400
803 #define FPU_CSR_OVF_E	0x00000200
804 #define FPU_CSR_UDF_E	0x00000100
805 #define FPU_CSR_INE_E	0x00000080
806 
807 #define FPU_CSR_ALL_S	0x0000007c
808 #define FPU_CSR_INV_S	0x00000040
809 #define FPU_CSR_DIV_S	0x00000020
810 #define FPU_CSR_OVF_S	0x00000010
811 #define FPU_CSR_UDF_S	0x00000008
812 #define FPU_CSR_INE_S	0x00000004
813 
814 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
815 #define FPU_CSR_RM	0x00000003
816 #define FPU_CSR_RN	0x0	/* nearest */
817 #define FPU_CSR_RZ	0x1	/* towards zero */
818 #define FPU_CSR_RU	0x2	/* towards +Infinity */
819 #define FPU_CSR_RD	0x3	/* towards -Infinity */
820 
821 
822 #ifndef __ASSEMBLY__
823 
824 /*
825  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
826  */
827 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
828 	defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
829 #define get_isa16_mode(x)		((x) & 0x1)
830 #define msk_isa16_mode(x)		((x) & ~0x1)
831 #define set_isa16_mode(x)		do { (x) |= 0x1; } while (0)
832 #else
833 #define get_isa16_mode(x)		0
834 #define msk_isa16_mode(x)		(x)
835 #define set_isa16_mode(x)		do { } while (0)
836 #endif
837 
838 /*
839  * microMIPS instructions can be 16-bit or 32-bit in length. This
840  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
841  */
842 static inline int mm_insn_16bit(u16 insn)
843 {
844 	u16 opcode = (insn >> 10) & 0x7;
845 
846 	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
847 }
848 
849 /*
850  * TLB Invalidate Flush
851  */
852 static inline void tlbinvf(void)
853 {
854 	__asm__ __volatile__(
855 		".set push\n\t"
856 		".set noreorder\n\t"
857 		".word 0x42000004\n\t" /* tlbinvf */
858 		".set pop");
859 }
860 
861 
862 /*
863  * Functions to access the R10000 performance counters.	 These are basically
864  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
865  * performance counter number encoded into bits 1 ... 5 of the instruction.
866  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
867  * disassembler these will look like an access to sel 0 or 1.
868  */
869 #define read_r10k_perf_cntr(counter)				\
870 ({								\
871 	unsigned int __res;					\
872 	__asm__ __volatile__(					\
873 	"mfpc\t%0, %1"						\
874 	: "=r" (__res)						\
875 	: "i" (counter));					\
876 								\
877 	__res;							\
878 })
879 
880 #define write_r10k_perf_cntr(counter,val)			\
881 do {								\
882 	__asm__ __volatile__(					\
883 	"mtpc\t%0, %1"						\
884 	:							\
885 	: "r" (val), "i" (counter));				\
886 } while (0)
887 
888 #define read_r10k_perf_event(counter)				\
889 ({								\
890 	unsigned int __res;					\
891 	__asm__ __volatile__(					\
892 	"mfps\t%0, %1"						\
893 	: "=r" (__res)						\
894 	: "i" (counter));					\
895 								\
896 	__res;							\
897 })
898 
899 #define write_r10k_perf_cntl(counter,val)			\
900 do {								\
901 	__asm__ __volatile__(					\
902 	"mtps\t%0, %1"						\
903 	:							\
904 	: "r" (val), "i" (counter));				\
905 } while (0)
906 
907 
908 /*
909  * Macros to access the system control coprocessor
910  */
911 
912 #define __read_32bit_c0_register(source, sel)				\
913 ({ unsigned int __res;							\
914 	if (sel == 0)							\
915 		__asm__ __volatile__(					\
916 			"mfc0\t%0, " #source "\n\t"			\
917 			: "=r" (__res));				\
918 	else								\
919 		__asm__ __volatile__(					\
920 			".set\tmips32\n\t"				\
921 			"mfc0\t%0, " #source ", " #sel "\n\t"		\
922 			".set\tmips0\n\t"				\
923 			: "=r" (__res));				\
924 	__res;								\
925 })
926 
927 #define __read_64bit_c0_register(source, sel)				\
928 ({ unsigned long long __res;						\
929 	if (sizeof(unsigned long) == 4)					\
930 		__res = __read_64bit_c0_split(source, sel);		\
931 	else if (sel == 0)						\
932 		__asm__ __volatile__(					\
933 			".set\tmips3\n\t"				\
934 			"dmfc0\t%0, " #source "\n\t"			\
935 			".set\tmips0"					\
936 			: "=r" (__res));				\
937 	else								\
938 		__asm__ __volatile__(					\
939 			".set\tmips64\n\t"				\
940 			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
941 			".set\tmips0"					\
942 			: "=r" (__res));				\
943 	__res;								\
944 })
945 
946 #define __write_32bit_c0_register(register, sel, value)			\
947 do {									\
948 	if (sel == 0)							\
949 		__asm__ __volatile__(					\
950 			"mtc0\t%z0, " #register "\n\t"			\
951 			: : "Jr" ((unsigned int)(value)));		\
952 	else								\
953 		__asm__ __volatile__(					\
954 			".set\tmips32\n\t"				\
955 			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
956 			".set\tmips0"					\
957 			: : "Jr" ((unsigned int)(value)));		\
958 } while (0)
959 
960 #define __write_64bit_c0_register(register, sel, value)			\
961 do {									\
962 	if (sizeof(unsigned long) == 4)					\
963 		__write_64bit_c0_split(register, sel, value);		\
964 	else if (sel == 0)						\
965 		__asm__ __volatile__(					\
966 			".set\tmips3\n\t"				\
967 			"dmtc0\t%z0, " #register "\n\t"			\
968 			".set\tmips0"					\
969 			: : "Jr" (value));				\
970 	else								\
971 		__asm__ __volatile__(					\
972 			".set\tmips64\n\t"				\
973 			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
974 			".set\tmips0"					\
975 			: : "Jr" (value));				\
976 } while (0)
977 
978 #define __read_ulong_c0_register(reg, sel)				\
979 	((sizeof(unsigned long) == 4) ?					\
980 	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
981 	(unsigned long) __read_64bit_c0_register(reg, sel))
982 
983 #define __write_ulong_c0_register(reg, sel, val)			\
984 do {									\
985 	if (sizeof(unsigned long) == 4)					\
986 		__write_32bit_c0_register(reg, sel, val);		\
987 	else								\
988 		__write_64bit_c0_register(reg, sel, val);		\
989 } while (0)
990 
991 /*
992  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
993  */
994 #define __read_32bit_c0_ctrl_register(source)				\
995 ({ unsigned int __res;							\
996 	__asm__ __volatile__(						\
997 		"cfc0\t%0, " #source "\n\t"				\
998 		: "=r" (__res));					\
999 	__res;								\
1000 })
1001 
1002 #define __write_32bit_c0_ctrl_register(register, value)			\
1003 do {									\
1004 	__asm__ __volatile__(						\
1005 		"ctc0\t%z0, " #register "\n\t"				\
1006 		: : "Jr" ((unsigned int)(value)));			\
1007 } while (0)
1008 
1009 /*
1010  * These versions are only needed for systems with more than 38 bits of
1011  * physical address space running the 32-bit kernel.  That's none atm :-)
1012  */
1013 #define __read_64bit_c0_split(source, sel)				\
1014 ({									\
1015 	unsigned long long __val;					\
1016 	unsigned long __flags;						\
1017 									\
1018 	local_irq_save(__flags);					\
1019 	if (sel == 0)							\
1020 		__asm__ __volatile__(					\
1021 			".set\tmips64\n\t"				\
1022 			"dmfc0\t%M0, " #source "\n\t"			\
1023 			"dsll\t%L0, %M0, 32\n\t"			\
1024 			"dsra\t%M0, %M0, 32\n\t"			\
1025 			"dsra\t%L0, %L0, 32\n\t"			\
1026 			".set\tmips0"					\
1027 			: "=r" (__val));				\
1028 	else								\
1029 		__asm__ __volatile__(					\
1030 			".set\tmips64\n\t"				\
1031 			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
1032 			"dsll\t%L0, %M0, 32\n\t"			\
1033 			"dsra\t%M0, %M0, 32\n\t"			\
1034 			"dsra\t%L0, %L0, 32\n\t"			\
1035 			".set\tmips0"					\
1036 			: "=r" (__val));				\
1037 	local_irq_restore(__flags);					\
1038 									\
1039 	__val;								\
1040 })
1041 
1042 #define __write_64bit_c0_split(source, sel, val)			\
1043 do {									\
1044 	unsigned long __flags;						\
1045 									\
1046 	local_irq_save(__flags);					\
1047 	if (sel == 0)							\
1048 		__asm__ __volatile__(					\
1049 			".set\tmips64\n\t"				\
1050 			"dsll\t%L0, %L0, 32\n\t"			\
1051 			"dsrl\t%L0, %L0, 32\n\t"			\
1052 			"dsll\t%M0, %M0, 32\n\t"			\
1053 			"or\t%L0, %L0, %M0\n\t"				\
1054 			"dmtc0\t%L0, " #source "\n\t"			\
1055 			".set\tmips0"					\
1056 			: : "r" (val));					\
1057 	else								\
1058 		__asm__ __volatile__(					\
1059 			".set\tmips64\n\t"				\
1060 			"dsll\t%L0, %L0, 32\n\t"			\
1061 			"dsrl\t%L0, %L0, 32\n\t"			\
1062 			"dsll\t%M0, %M0, 32\n\t"			\
1063 			"or\t%L0, %L0, %M0\n\t"				\
1064 			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1065 			".set\tmips0"					\
1066 			: : "r" (val));					\
1067 	local_irq_restore(__flags);					\
1068 } while (0)
1069 
1070 #define __readx_32bit_c0_register(source)				\
1071 ({									\
1072 	unsigned int __res;						\
1073 									\
1074 	__asm__ __volatile__(						\
1075 	"	.set	push					\n"	\
1076 	"	.set	noat					\n"	\
1077 	"	.set	mips32r2				\n"	\
1078 	"	.insn						\n"	\
1079 	"	# mfhc0 $1, %1					\n"	\
1080 	"	.word	(0x40410000 | ((%1 & 0x1f) << 11))	\n"	\
1081 	"	move	%0, $1					\n"	\
1082 	"	.set	pop					\n"	\
1083 	: "=r" (__res)							\
1084 	: "i" (source));						\
1085 	__res;								\
1086 })
1087 
1088 #define __writex_32bit_c0_register(register, value)			\
1089 ({									\
1090 	__asm__ __volatile__(						\
1091 	"	.set	push					\n"	\
1092 	"	.set	noat					\n"	\
1093 	"	.set	mips32r2				\n"	\
1094 	"	move	$1, %0					\n"	\
1095 	"	# mthc0 $1, %1					\n"	\
1096 	"	.insn						\n"	\
1097 	"	.word	(0x40c10000 | ((%1 & 0x1f) << 11))	\n"	\
1098 	"	.set	pop					\n"	\
1099 	:								\
1100 	: "r" (value), "i" (register));					\
1101 })
1102 
1103 #define read_c0_index()		__read_32bit_c0_register($0, 0)
1104 #define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
1105 
1106 #define read_c0_random()	__read_32bit_c0_register($1, 0)
1107 #define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
1108 
1109 #define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
1110 #define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
1111 
1112 #define readx_c0_entrylo0()	__readx_32bit_c0_register(2)
1113 #define writex_c0_entrylo0(val)	__writex_32bit_c0_register(2, val)
1114 
1115 #define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
1116 #define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
1117 
1118 #define readx_c0_entrylo1()	__readx_32bit_c0_register(3)
1119 #define writex_c0_entrylo1(val)	__writex_32bit_c0_register(3, val)
1120 
1121 #define read_c0_conf()		__read_32bit_c0_register($3, 0)
1122 #define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
1123 
1124 #define read_c0_context()	__read_ulong_c0_register($4, 0)
1125 #define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
1126 
1127 #define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
1128 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1129 
1130 #define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
1131 #define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
1132 
1133 #define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
1134 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1135 
1136 #define read_c0_wired()		__read_32bit_c0_register($6, 0)
1137 #define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
1138 
1139 #define read_c0_info()		__read_32bit_c0_register($7, 0)
1140 
1141 #define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
1142 #define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
1143 
1144 #define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
1145 #define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
1146 
1147 #define read_c0_count()		__read_32bit_c0_register($9, 0)
1148 #define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
1149 
1150 #define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
1151 #define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
1152 
1153 #define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
1154 #define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
1155 
1156 #define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
1157 #define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
1158 
1159 #define read_c0_compare()	__read_32bit_c0_register($11, 0)
1160 #define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
1161 
1162 #define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
1163 #define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
1164 
1165 #define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
1166 #define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
1167 
1168 #define read_c0_status()	__read_32bit_c0_register($12, 0)
1169 
1170 #define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
1171 
1172 #define read_c0_cause()		__read_32bit_c0_register($13, 0)
1173 #define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
1174 
1175 #define read_c0_epc()		__read_ulong_c0_register($14, 0)
1176 #define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
1177 
1178 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
1179 
1180 #define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
1181 
1182 #define read_c0_config()	__read_32bit_c0_register($16, 0)
1183 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
1184 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
1185 #define read_c0_config3()	__read_32bit_c0_register($16, 3)
1186 #define read_c0_config4()	__read_32bit_c0_register($16, 4)
1187 #define read_c0_config5()	__read_32bit_c0_register($16, 5)
1188 #define read_c0_config6()	__read_32bit_c0_register($16, 6)
1189 #define read_c0_config7()	__read_32bit_c0_register($16, 7)
1190 #define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
1191 #define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
1192 #define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
1193 #define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
1194 #define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
1195 #define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
1196 #define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
1197 #define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
1198 
1199 #define read_c0_lladdr()	__read_ulong_c0_register($17, 0)
1200 #define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
1201 #define read_c0_maar()		__read_ulong_c0_register($17, 1)
1202 #define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
1203 #define read_c0_maari()		__read_32bit_c0_register($17, 2)
1204 #define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
1205 
1206 /*
1207  * The WatchLo register.  There may be up to 8 of them.
1208  */
1209 #define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
1210 #define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
1211 #define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
1212 #define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
1213 #define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
1214 #define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
1215 #define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
1216 #define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
1217 #define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
1218 #define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
1219 #define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
1220 #define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
1221 #define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
1222 #define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
1223 #define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
1224 #define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
1225 
1226 /*
1227  * The WatchHi register.  There may be up to 8 of them.
1228  */
1229 #define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
1230 #define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
1231 #define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
1232 #define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
1233 #define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
1234 #define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
1235 #define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
1236 #define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
1237 
1238 #define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
1239 #define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
1240 #define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
1241 #define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
1242 #define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
1243 #define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
1244 #define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
1245 #define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
1246 
1247 #define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
1248 #define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
1249 
1250 #define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
1251 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1252 
1253 #define read_c0_framemask()	__read_32bit_c0_register($21, 0)
1254 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1255 
1256 #define read_c0_diag()		__read_32bit_c0_register($22, 0)
1257 #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
1258 
1259 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1260 #define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
1261 #define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)
1262 
1263 #define read_c0_diag1()		__read_32bit_c0_register($22, 1)
1264 #define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
1265 
1266 #define read_c0_diag2()		__read_32bit_c0_register($22, 2)
1267 #define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
1268 
1269 #define read_c0_diag3()		__read_32bit_c0_register($22, 3)
1270 #define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
1271 
1272 #define read_c0_diag4()		__read_32bit_c0_register($22, 4)
1273 #define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
1274 
1275 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
1276 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
1277 
1278 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
1279 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
1280 
1281 #define read_c0_depc()		__read_ulong_c0_register($24, 0)
1282 #define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
1283 
1284 /*
1285  * MIPS32 / MIPS64 performance counters
1286  */
1287 #define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
1288 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1289 #define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
1290 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1291 #define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
1292 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1293 #define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
1294 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1295 #define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
1296 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1297 #define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
1298 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1299 #define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
1300 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1301 #define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
1302 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1303 #define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
1304 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1305 #define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
1306 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1307 #define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
1308 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1309 #define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
1310 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1311 
1312 #define read_c0_ecc()		__read_32bit_c0_register($26, 0)
1313 #define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
1314 
1315 #define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
1316 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1317 
1318 #define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
1319 
1320 #define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
1321 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1322 
1323 #define read_c0_taglo()		__read_32bit_c0_register($28, 0)
1324 #define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
1325 
1326 #define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
1327 #define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
1328 
1329 #define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
1330 #define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)
1331 
1332 #define read_c0_staglo()	__read_32bit_c0_register($28, 4)
1333 #define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)
1334 
1335 #define read_c0_taghi()		__read_32bit_c0_register($29, 0)
1336 #define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
1337 
1338 #define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
1339 #define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
1340 
1341 /* MIPSR2 */
1342 #define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
1343 #define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
1344 
1345 #define read_c0_intctl()	__read_32bit_c0_register($12, 1)
1346 #define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
1347 
1348 #define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
1349 #define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
1350 
1351 #define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
1352 #define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
1353 
1354 #define read_c0_ebase()		__read_32bit_c0_register($15, 1)
1355 #define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
1356 
1357 #define read_c0_cdmmbase()	__read_ulong_c0_register($15, 2)
1358 #define write_c0_cdmmbase(val)	__write_ulong_c0_register($15, 2, val)
1359 
1360 /* MIPSR3 */
1361 #define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
1362 #define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
1363 
1364 #define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
1365 #define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
1366 
1367 #define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
1368 #define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
1369 
1370 /* Hardware Page Table Walker */
1371 #define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
1372 #define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)
1373 
1374 #define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
1375 #define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)
1376 
1377 #define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
1378 #define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)
1379 
1380 #define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
1381 #define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)
1382 
1383 /* Cavium OCTEON (cnMIPS) */
1384 #define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
1385 #define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)
1386 
1387 #define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
1388 #define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)
1389 
1390 #define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
1391 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1392 /*
1393  * The cacheerr registers are not standardized.	 On OCTEON, they are
1394  * 64 bits wide.
1395  */
1396 #define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
1397 #define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)
1398 
1399 #define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
1400 #define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)
1401 
1402 /* BMIPS3300 */
1403 #define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
1404 #define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
1405 
1406 #define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
1407 #define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
1408 
1409 #define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
1410 #define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
1411 
1412 /* BMIPS43xx */
1413 #define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
1414 #define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
1415 
1416 #define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
1417 #define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
1418 
1419 #define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
1420 #define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
1421 
1422 #define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
1423 #define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
1424 
1425 #define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
1426 #define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
1427 
1428 /* BMIPS5000 */
1429 #define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
1430 #define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
1431 
1432 #define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
1433 #define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
1434 
1435 #define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
1436 #define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
1437 
1438 #define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
1439 #define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
1440 
1441 #define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
1442 #define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
1443 
1444 #define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
1445 #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
1446 
1447 /*
1448  * Macros to access the floating point coprocessor control registers
1449  */
1450 #define _read_32bit_cp1_register(source, gas_hardfloat)			\
1451 ({									\
1452 	unsigned int __res;						\
1453 									\
1454 	__asm__ __volatile__(						\
1455 	"	.set	push					\n"	\
1456 	"	.set	reorder					\n"	\
1457 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
1458 	"	# like Octeon.					\n"	\
1459 	"	.set	mips1					\n"	\
1460 	"	"STR(gas_hardfloat)"				\n"	\
1461 	"	cfc1	%0,"STR(source)"			\n"	\
1462 	"	.set	pop					\n"	\
1463 	: "=r" (__res));						\
1464 	__res;								\
1465 })
1466 
1467 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)		\
1468 ({									\
1469 	__asm__ __volatile__(						\
1470 	"	.set	push					\n"	\
1471 	"	.set	reorder					\n"	\
1472 	"	"STR(gas_hardfloat)"				\n"	\
1473 	"	ctc1	%0,"STR(dest)"				\n"	\
1474 	"	.set	pop					\n"	\
1475 	: : "r" (val));							\
1476 })
1477 
1478 #ifdef GAS_HAS_SET_HARDFLOAT
1479 #define read_32bit_cp1_register(source)					\
1480 	_read_32bit_cp1_register(source, .set hardfloat)
1481 #define write_32bit_cp1_register(dest, val)				\
1482 	_write_32bit_cp1_register(dest, val, .set hardfloat)
1483 #else
1484 #define read_32bit_cp1_register(source)					\
1485 	_read_32bit_cp1_register(source, )
1486 #define write_32bit_cp1_register(dest, val)				\
1487 	_write_32bit_cp1_register(dest, val, )
1488 #endif
1489 
1490 #ifdef HAVE_AS_DSP
1491 #define rddsp(mask)							\
1492 ({									\
1493 	unsigned int __dspctl;						\
1494 									\
1495 	__asm__ __volatile__(						\
1496 	"	.set push					\n"	\
1497 	"	.set dsp					\n"	\
1498 	"	rddsp	%0, %x1					\n"	\
1499 	"	.set pop					\n"	\
1500 	: "=r" (__dspctl)						\
1501 	: "i" (mask));							\
1502 	__dspctl;							\
1503 })
1504 
1505 #define wrdsp(val, mask)						\
1506 ({									\
1507 	__asm__ __volatile__(						\
1508 	"	.set push					\n"	\
1509 	"	.set dsp					\n"	\
1510 	"	wrdsp	%0, %x1					\n"	\
1511 	"	.set pop					\n"	\
1512 	:								\
1513 	: "r" (val), "i" (mask));					\
1514 })
1515 
1516 #define mflo0()								\
1517 ({									\
1518 	long mflo0;							\
1519 	__asm__(							\
1520 	"	.set push					\n"	\
1521 	"	.set dsp					\n"	\
1522 	"	mflo %0, $ac0					\n"	\
1523 	"	.set pop					\n"	\
1524 	: "=r" (mflo0));						\
1525 	mflo0;								\
1526 })
1527 
1528 #define mflo1()								\
1529 ({									\
1530 	long mflo1;							\
1531 	__asm__(							\
1532 	"	.set push					\n"	\
1533 	"	.set dsp					\n"	\
1534 	"	mflo %0, $ac1					\n"	\
1535 	"	.set pop					\n"	\
1536 	: "=r" (mflo1));						\
1537 	mflo1;								\
1538 })
1539 
1540 #define mflo2()								\
1541 ({									\
1542 	long mflo2;							\
1543 	__asm__(							\
1544 	"	.set push					\n"	\
1545 	"	.set dsp					\n"	\
1546 	"	mflo %0, $ac2					\n"	\
1547 	"	.set pop					\n"	\
1548 	: "=r" (mflo2));						\
1549 	mflo2;								\
1550 })
1551 
1552 #define mflo3()								\
1553 ({									\
1554 	long mflo3;							\
1555 	__asm__(							\
1556 	"	.set push					\n"	\
1557 	"	.set dsp					\n"	\
1558 	"	mflo %0, $ac3					\n"	\
1559 	"	.set pop					\n"	\
1560 	: "=r" (mflo3));						\
1561 	mflo3;								\
1562 })
1563 
1564 #define mfhi0()								\
1565 ({									\
1566 	long mfhi0;							\
1567 	__asm__(							\
1568 	"	.set push					\n"	\
1569 	"	.set dsp					\n"	\
1570 	"	mfhi %0, $ac0					\n"	\
1571 	"	.set pop					\n"	\
1572 	: "=r" (mfhi0));						\
1573 	mfhi0;								\
1574 })
1575 
1576 #define mfhi1()								\
1577 ({									\
1578 	long mfhi1;							\
1579 	__asm__(							\
1580 	"	.set push					\n"	\
1581 	"	.set dsp					\n"	\
1582 	"	mfhi %0, $ac1					\n"	\
1583 	"	.set pop					\n"	\
1584 	: "=r" (mfhi1));						\
1585 	mfhi1;								\
1586 })
1587 
1588 #define mfhi2()								\
1589 ({									\
1590 	long mfhi2;							\
1591 	__asm__(							\
1592 	"	.set push					\n"	\
1593 	"	.set dsp					\n"	\
1594 	"	mfhi %0, $ac2					\n"	\
1595 	"	.set pop					\n"	\
1596 	: "=r" (mfhi2));						\
1597 	mfhi2;								\
1598 })
1599 
1600 #define mfhi3()								\
1601 ({									\
1602 	long mfhi3;							\
1603 	__asm__(							\
1604 	"	.set push					\n"	\
1605 	"	.set dsp					\n"	\
1606 	"	mfhi %0, $ac3					\n"	\
1607 	"	.set pop					\n"	\
1608 	: "=r" (mfhi3));						\
1609 	mfhi3;								\
1610 })
1611 
1612 
1613 #define mtlo0(x)							\
1614 ({									\
1615 	__asm__(							\
1616 	"	.set push					\n"	\
1617 	"	.set dsp					\n"	\
1618 	"	mtlo %0, $ac0					\n"	\
1619 	"	.set pop					\n"	\
1620 	:								\
1621 	: "r" (x));							\
1622 })
1623 
1624 #define mtlo1(x)							\
1625 ({									\
1626 	__asm__(							\
1627 	"	.set push					\n"	\
1628 	"	.set dsp					\n"	\
1629 	"	mtlo %0, $ac1					\n"	\
1630 	"	.set pop					\n"	\
1631 	:								\
1632 	: "r" (x));							\
1633 })
1634 
1635 #define mtlo2(x)							\
1636 ({									\
1637 	__asm__(							\
1638 	"	.set push					\n"	\
1639 	"	.set dsp					\n"	\
1640 	"	mtlo %0, $ac2					\n"	\
1641 	"	.set pop					\n"	\
1642 	:								\
1643 	: "r" (x));							\
1644 })
1645 
1646 #define mtlo3(x)							\
1647 ({									\
1648 	__asm__(							\
1649 	"	.set push					\n"	\
1650 	"	.set dsp					\n"	\
1651 	"	mtlo %0, $ac3					\n"	\
1652 	"	.set pop					\n"	\
1653 	:								\
1654 	: "r" (x));							\
1655 })
1656 
1657 #define mthi0(x)							\
1658 ({									\
1659 	__asm__(							\
1660 	"	.set push					\n"	\
1661 	"	.set dsp					\n"	\
1662 	"	mthi %0, $ac0					\n"	\
1663 	"	.set pop					\n"	\
1664 	:								\
1665 	: "r" (x));							\
1666 })
1667 
1668 #define mthi1(x)							\
1669 ({									\
1670 	__asm__(							\
1671 	"	.set push					\n"	\
1672 	"	.set dsp					\n"	\
1673 	"	mthi %0, $ac1					\n"	\
1674 	"	.set pop					\n"	\
1675 	:								\
1676 	: "r" (x));							\
1677 })
1678 
1679 #define mthi2(x)							\
1680 ({									\
1681 	__asm__(							\
1682 	"	.set push					\n"	\
1683 	"	.set dsp					\n"	\
1684 	"	mthi %0, $ac2					\n"	\
1685 	"	.set pop					\n"	\
1686 	:								\
1687 	: "r" (x));							\
1688 })
1689 
1690 #define mthi3(x)							\
1691 ({									\
1692 	__asm__(							\
1693 	"	.set push					\n"	\
1694 	"	.set dsp					\n"	\
1695 	"	mthi %0, $ac3					\n"	\
1696 	"	.set pop					\n"	\
1697 	:								\
1698 	: "r" (x));							\
1699 })
1700 
1701 #else
1702 
1703 #ifdef CONFIG_CPU_MICROMIPS
1704 #define rddsp(mask)							\
1705 ({									\
1706 	unsigned int __res;						\
1707 									\
1708 	__asm__ __volatile__(						\
1709 	"	.set	push					\n"	\
1710 	"	.set	noat					\n"	\
1711 	"	# rddsp $1, %x1					\n"	\
1712 	"	.hword	((0x0020067c | (%x1 << 14)) >> 16)	\n"	\
1713 	"	.hword	((0x0020067c | (%x1 << 14)) & 0xffff)	\n"	\
1714 	"	move	%0, $1					\n"	\
1715 	"	.set	pop					\n"	\
1716 	: "=r" (__res)							\
1717 	: "i" (mask));							\
1718 	__res;								\
1719 })
1720 
1721 #define wrdsp(val, mask)						\
1722 ({									\
1723 	__asm__ __volatile__(						\
1724 	"	.set	push					\n"	\
1725 	"	.set	noat					\n"	\
1726 	"	move	$1, %0					\n"	\
1727 	"	# wrdsp $1, %x1					\n"	\
1728 	"	.hword	((0x0020167c | (%x1 << 14)) >> 16)	\n"	\
1729 	"	.hword	((0x0020167c | (%x1 << 14)) & 0xffff)	\n"	\
1730 	"	.set	pop					\n"	\
1731 	:								\
1732 	: "r" (val), "i" (mask));					\
1733 })
1734 
1735 #define _umips_dsp_mfxxx(ins)						\
1736 ({									\
1737 	unsigned long __treg;						\
1738 									\
1739 	__asm__ __volatile__(						\
1740 	"	.set	push					\n"	\
1741 	"	.set	noat					\n"	\
1742 	"	.hword	0x0001					\n"	\
1743 	"	.hword	%x1					\n"	\
1744 	"	move	%0, $1					\n"	\
1745 	"	.set	pop					\n"	\
1746 	: "=r" (__treg)							\
1747 	: "i" (ins));							\
1748 	__treg;								\
1749 })
1750 
1751 #define _umips_dsp_mtxxx(val, ins)					\
1752 ({									\
1753 	__asm__ __volatile__(						\
1754 	"	.set	push					\n"	\
1755 	"	.set	noat					\n"	\
1756 	"	move	$1, %0					\n"	\
1757 	"	.hword	0x0001					\n"	\
1758 	"	.hword	%x1					\n"	\
1759 	"	.set	pop					\n"	\
1760 	:								\
1761 	: "r" (val), "i" (ins));					\
1762 })
1763 
1764 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1765 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1766 
1767 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1768 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1769 
1770 #define mflo0() _umips_dsp_mflo(0)
1771 #define mflo1() _umips_dsp_mflo(1)
1772 #define mflo2() _umips_dsp_mflo(2)
1773 #define mflo3() _umips_dsp_mflo(3)
1774 
1775 #define mfhi0() _umips_dsp_mfhi(0)
1776 #define mfhi1() _umips_dsp_mfhi(1)
1777 #define mfhi2() _umips_dsp_mfhi(2)
1778 #define mfhi3() _umips_dsp_mfhi(3)
1779 
1780 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1781 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1782 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1783 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1784 
1785 #define mthi0(x) _umips_dsp_mthi(x, 0)
1786 #define mthi1(x) _umips_dsp_mthi(x, 1)
1787 #define mthi2(x) _umips_dsp_mthi(x, 2)
1788 #define mthi3(x) _umips_dsp_mthi(x, 3)
1789 
1790 #else  /* !CONFIG_CPU_MICROMIPS */
1791 #define rddsp(mask)							\
1792 ({									\
1793 	unsigned int __res;						\
1794 									\
1795 	__asm__ __volatile__(						\
1796 	"	.set	push				\n"		\
1797 	"	.set	noat				\n"		\
1798 	"	# rddsp $1, %x1				\n"		\
1799 	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
1800 	"	move	%0, $1				\n"		\
1801 	"	.set	pop				\n"		\
1802 	: "=r" (__res)							\
1803 	: "i" (mask));							\
1804 	__res;								\
1805 })
1806 
1807 #define wrdsp(val, mask)						\
1808 ({									\
1809 	__asm__ __volatile__(						\
1810 	"	.set	push					\n"	\
1811 	"	.set	noat					\n"	\
1812 	"	move	$1, %0					\n"	\
1813 	"	# wrdsp $1, %x1					\n"	\
1814 	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
1815 	"	.set	pop					\n"	\
1816 	:								\
1817 	: "r" (val), "i" (mask));					\
1818 })
1819 
1820 #define _dsp_mfxxx(ins)							\
1821 ({									\
1822 	unsigned long __treg;						\
1823 									\
1824 	__asm__ __volatile__(						\
1825 	"	.set	push					\n"	\
1826 	"	.set	noat					\n"	\
1827 	"	.word	(0x00000810 | %1)			\n"	\
1828 	"	move	%0, $1					\n"	\
1829 	"	.set	pop					\n"	\
1830 	: "=r" (__treg)							\
1831 	: "i" (ins));							\
1832 	__treg;								\
1833 })
1834 
1835 #define _dsp_mtxxx(val, ins)						\
1836 ({									\
1837 	__asm__ __volatile__(						\
1838 	"	.set	push					\n"	\
1839 	"	.set	noat					\n"	\
1840 	"	move	$1, %0					\n"	\
1841 	"	.word	(0x00200011 | %1)			\n"	\
1842 	"	.set	pop					\n"	\
1843 	:								\
1844 	: "r" (val), "i" (ins));					\
1845 })
1846 
1847 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1848 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1849 
1850 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1851 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1852 
1853 #define mflo0() _dsp_mflo(0)
1854 #define mflo1() _dsp_mflo(1)
1855 #define mflo2() _dsp_mflo(2)
1856 #define mflo3() _dsp_mflo(3)
1857 
1858 #define mfhi0() _dsp_mfhi(0)
1859 #define mfhi1() _dsp_mfhi(1)
1860 #define mfhi2() _dsp_mfhi(2)
1861 #define mfhi3() _dsp_mfhi(3)
1862 
1863 #define mtlo0(x) _dsp_mtlo(x, 0)
1864 #define mtlo1(x) _dsp_mtlo(x, 1)
1865 #define mtlo2(x) _dsp_mtlo(x, 2)
1866 #define mtlo3(x) _dsp_mtlo(x, 3)
1867 
1868 #define mthi0(x) _dsp_mthi(x, 0)
1869 #define mthi1(x) _dsp_mthi(x, 1)
1870 #define mthi2(x) _dsp_mthi(x, 2)
1871 #define mthi3(x) _dsp_mthi(x, 3)
1872 
1873 #endif /* CONFIG_CPU_MICROMIPS */
1874 #endif
1875 
1876 /*
1877  * TLB operations.
1878  *
1879  * It is responsibility of the caller to take care of any TLB hazards.
1880  */
1881 static inline void tlb_probe(void)
1882 {
1883 	__asm__ __volatile__(
1884 		".set noreorder\n\t"
1885 		"tlbp\n\t"
1886 		".set reorder");
1887 }
1888 
1889 static inline void tlb_read(void)
1890 {
1891 #if MIPS34K_MISSED_ITLB_WAR
1892 	int res = 0;
1893 
1894 	__asm__ __volatile__(
1895 	"	.set	push					\n"
1896 	"	.set	noreorder				\n"
1897 	"	.set	noat					\n"
1898 	"	.set	mips32r2				\n"
1899 	"	.word	0x41610001		# dvpe $1	\n"
1900 	"	move	%0, $1					\n"
1901 	"	ehb						\n"
1902 	"	.set	pop					\n"
1903 	: "=r" (res));
1904 
1905 	instruction_hazard();
1906 #endif
1907 
1908 	__asm__ __volatile__(
1909 		".set noreorder\n\t"
1910 		"tlbr\n\t"
1911 		".set reorder");
1912 
1913 #if MIPS34K_MISSED_ITLB_WAR
1914 	if ((res & _ULCAST_(1)))
1915 		__asm__ __volatile__(
1916 		"	.set	push				\n"
1917 		"	.set	noreorder			\n"
1918 		"	.set	noat				\n"
1919 		"	.set	mips32r2			\n"
1920 		"	.word	0x41600021	# evpe		\n"
1921 		"	ehb					\n"
1922 		"	.set	pop				\n");
1923 #endif
1924 }
1925 
1926 static inline void tlb_write_indexed(void)
1927 {
1928 	__asm__ __volatile__(
1929 		".set noreorder\n\t"
1930 		"tlbwi\n\t"
1931 		".set reorder");
1932 }
1933 
1934 static inline void tlb_write_random(void)
1935 {
1936 	__asm__ __volatile__(
1937 		".set noreorder\n\t"
1938 		"tlbwr\n\t"
1939 		".set reorder");
1940 }
1941 
1942 /*
1943  * Manipulate bits in a c0 register.
1944  */
1945 #define __BUILD_SET_C0(name)					\
1946 static inline unsigned int					\
1947 set_c0_##name(unsigned int set)					\
1948 {								\
1949 	unsigned int res, new;					\
1950 								\
1951 	res = read_c0_##name();					\
1952 	new = res | set;					\
1953 	write_c0_##name(new);					\
1954 								\
1955 	return res;						\
1956 }								\
1957 								\
1958 static inline unsigned int					\
1959 clear_c0_##name(unsigned int clear)				\
1960 {								\
1961 	unsigned int res, new;					\
1962 								\
1963 	res = read_c0_##name();					\
1964 	new = res & ~clear;					\
1965 	write_c0_##name(new);					\
1966 								\
1967 	return res;						\
1968 }								\
1969 								\
1970 static inline unsigned int					\
1971 change_c0_##name(unsigned int change, unsigned int val)		\
1972 {								\
1973 	unsigned int res, new;					\
1974 								\
1975 	res = read_c0_##name();					\
1976 	new = res & ~change;					\
1977 	new |= (val & change);					\
1978 	write_c0_##name(new);					\
1979 								\
1980 	return res;						\
1981 }
1982 
1983 __BUILD_SET_C0(status)
1984 __BUILD_SET_C0(cause)
1985 __BUILD_SET_C0(config)
1986 __BUILD_SET_C0(config5)
1987 __BUILD_SET_C0(intcontrol)
1988 __BUILD_SET_C0(intctl)
1989 __BUILD_SET_C0(srsmap)
1990 __BUILD_SET_C0(pagegrain)
1991 __BUILD_SET_C0(brcm_config_0)
1992 __BUILD_SET_C0(brcm_bus_pll)
1993 __BUILD_SET_C0(brcm_reset)
1994 __BUILD_SET_C0(brcm_cmt_intr)
1995 __BUILD_SET_C0(brcm_cmt_ctrl)
1996 __BUILD_SET_C0(brcm_config)
1997 __BUILD_SET_C0(brcm_mode)
1998 
1999 /*
2000  * Return low 10 bits of ebase.
2001  * Note that under KVM (MIPSVZ) this returns vcpu id.
2002  */
2003 static inline unsigned int get_ebase_cpunum(void)
2004 {
2005 	return read_c0_ebase() & 0x3ff;
2006 }
2007 
2008 #endif /* !__ASSEMBLY__ */
2009 
2010 #endif /* _ASM_MIPSREGS_H */
2011