1 /* 2 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 3 * Copyright (C) 2000 Silicon Graphics, Inc. 4 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 5 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 * Copyright (C) 2003, 2004 Maciej W. Rozycki 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 #ifndef _ASM_MIPSREGS_H 12 #define _ASM_MIPSREGS_H 13 14 /* 15 * The following macros are especially useful for __asm__ 16 * inline assembler. 17 */ 18 #ifndef __STR 19 #define __STR(x) #x 20 #endif 21 #ifndef STR 22 #define STR(x) __STR(x) 23 #endif 24 25 /* 26 * Configure language 27 */ 28 #ifdef __ASSEMBLY__ 29 #define _ULCAST_ 30 #else 31 #define _ULCAST_ (unsigned long) 32 #endif 33 34 /* 35 * Coprocessor 0 register names 36 */ 37 #define CP0_INDEX $0 38 #define CP0_RANDOM $1 39 #define CP0_ENTRYLO0 $2 40 #define CP0_ENTRYLO1 $3 41 #define CP0_CONF $3 42 #define CP0_CONTEXT $4 43 #define CP0_PAGEMASK $5 44 #define CP0_WIRED $6 45 #define CP0_INFO $7 46 #define CP0_HWRENA $7, 0 47 #define CP0_BADVADDR $8 48 #define CP0_BADINSTR $8, 1 49 #define CP0_COUNT $9 50 #define CP0_ENTRYHI $10 51 #define CP0_COMPARE $11 52 #define CP0_STATUS $12 53 #define CP0_CAUSE $13 54 #define CP0_EPC $14 55 #define CP0_PRID $15 56 #define CP0_EBASE $15, 1 57 #define CP0_CMGCRBASE $15, 3 58 #define CP0_CONFIG $16 59 #define CP0_CONFIG3 $16, 3 60 #define CP0_CONFIG5 $16, 5 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 114 /* Generic EntryLo bit definitions */ 115 #define ENTRYLO_G (_ULCAST_(1) << 0) 116 #define ENTRYLO_V (_ULCAST_(1) << 1) 117 #define ENTRYLO_D (_ULCAST_(1) << 2) 118 #define ENTRYLO_C_SHIFT 3 119 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) 120 121 /* R3000 EntryLo bit definitions */ 122 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8) 123 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9) 124 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10) 125 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11) 126 127 /* MIPS32/64 EntryLo bit definitions */ 128 #define MIPS_ENTRYLO_PFN_SHIFT 6 129 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2)) 130 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1)) 131 132 /* 133 * Values for PageMask register 134 */ 135 #ifdef CONFIG_CPU_VR41XX 136 137 /* Why doesn't stupidity hurt ... */ 138 139 #define PM_1K 0x00000000 140 #define PM_4K 0x00001800 141 #define PM_16K 0x00007800 142 #define PM_64K 0x0001f800 143 #define PM_256K 0x0007f800 144 145 #else 146 147 #define PM_4K 0x00000000 148 #define PM_8K 0x00002000 149 #define PM_16K 0x00006000 150 #define PM_32K 0x0000e000 151 #define PM_64K 0x0001e000 152 #define PM_128K 0x0003e000 153 #define PM_256K 0x0007e000 154 #define PM_512K 0x000fe000 155 #define PM_1M 0x001fe000 156 #define PM_2M 0x003fe000 157 #define PM_4M 0x007fe000 158 #define PM_8M 0x00ffe000 159 #define PM_16M 0x01ffe000 160 #define PM_32M 0x03ffe000 161 #define PM_64M 0x07ffe000 162 #define PM_256M 0x1fffe000 163 #define PM_1G 0x7fffe000 164 165 #endif 166 167 /* 168 * Values used for computation of new tlb entries 169 */ 170 #define PL_4K 12 171 #define PL_16K 14 172 #define PL_64K 16 173 #define PL_256K 18 174 #define PL_1M 20 175 #define PL_4M 22 176 #define PL_16M 24 177 #define PL_64M 26 178 #define PL_256M 28 179 180 /* 181 * PageGrain bits 182 */ 183 #define PG_RIE (_ULCAST_(1) << 31) 184 #define PG_XIE (_ULCAST_(1) << 30) 185 #define PG_ELPA (_ULCAST_(1) << 29) 186 #define PG_ESP (_ULCAST_(1) << 28) 187 #define PG_IEC (_ULCAST_(1) << 27) 188 189 /* MIPS32/64 EntryHI bit definitions */ 190 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 191 192 /* 193 * R4x00 interrupt enable / cause bits 194 */ 195 #define IE_SW0 (_ULCAST_(1) << 8) 196 #define IE_SW1 (_ULCAST_(1) << 9) 197 #define IE_IRQ0 (_ULCAST_(1) << 10) 198 #define IE_IRQ1 (_ULCAST_(1) << 11) 199 #define IE_IRQ2 (_ULCAST_(1) << 12) 200 #define IE_IRQ3 (_ULCAST_(1) << 13) 201 #define IE_IRQ4 (_ULCAST_(1) << 14) 202 #define IE_IRQ5 (_ULCAST_(1) << 15) 203 204 /* 205 * R4x00 interrupt cause bits 206 */ 207 #define C_SW0 (_ULCAST_(1) << 8) 208 #define C_SW1 (_ULCAST_(1) << 9) 209 #define C_IRQ0 (_ULCAST_(1) << 10) 210 #define C_IRQ1 (_ULCAST_(1) << 11) 211 #define C_IRQ2 (_ULCAST_(1) << 12) 212 #define C_IRQ3 (_ULCAST_(1) << 13) 213 #define C_IRQ4 (_ULCAST_(1) << 14) 214 #define C_IRQ5 (_ULCAST_(1) << 15) 215 216 /* 217 * Bitfields in the R4xx0 cp0 status register 218 */ 219 #define ST0_IE 0x00000001 220 #define ST0_EXL 0x00000002 221 #define ST0_ERL 0x00000004 222 #define ST0_KSU 0x00000018 223 # define KSU_USER 0x00000010 224 # define KSU_SUPERVISOR 0x00000008 225 # define KSU_KERNEL 0x00000000 226 #define ST0_UX 0x00000020 227 #define ST0_SX 0x00000040 228 #define ST0_KX 0x00000080 229 #define ST0_DE 0x00010000 230 #define ST0_CE 0x00020000 231 232 /* 233 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 234 * cacheops in userspace. This bit exists only on RM7000 and RM9000 235 * processors. 236 */ 237 #define ST0_CO 0x08000000 238 239 /* 240 * Bitfields in the R[23]000 cp0 status register. 241 */ 242 #define ST0_IEC 0x00000001 243 #define ST0_KUC 0x00000002 244 #define ST0_IEP 0x00000004 245 #define ST0_KUP 0x00000008 246 #define ST0_IEO 0x00000010 247 #define ST0_KUO 0x00000020 248 /* bits 6 & 7 are reserved on R[23]000 */ 249 #define ST0_ISC 0x00010000 250 #define ST0_SWC 0x00020000 251 #define ST0_CM 0x00080000 252 253 /* 254 * Bits specific to the R4640/R4650 255 */ 256 #define ST0_UM (_ULCAST_(1) << 4) 257 #define ST0_IL (_ULCAST_(1) << 23) 258 #define ST0_DL (_ULCAST_(1) << 24) 259 260 /* 261 * Enable the MIPS MDMX and DSP ASEs 262 */ 263 #define ST0_MX 0x01000000 264 265 /* 266 * Status register bits available in all MIPS CPUs. 267 */ 268 #define ST0_IM 0x0000ff00 269 #define STATUSB_IP0 8 270 #define STATUSF_IP0 (_ULCAST_(1) << 8) 271 #define STATUSB_IP1 9 272 #define STATUSF_IP1 (_ULCAST_(1) << 9) 273 #define STATUSB_IP2 10 274 #define STATUSF_IP2 (_ULCAST_(1) << 10) 275 #define STATUSB_IP3 11 276 #define STATUSF_IP3 (_ULCAST_(1) << 11) 277 #define STATUSB_IP4 12 278 #define STATUSF_IP4 (_ULCAST_(1) << 12) 279 #define STATUSB_IP5 13 280 #define STATUSF_IP5 (_ULCAST_(1) << 13) 281 #define STATUSB_IP6 14 282 #define STATUSF_IP6 (_ULCAST_(1) << 14) 283 #define STATUSB_IP7 15 284 #define STATUSF_IP7 (_ULCAST_(1) << 15) 285 #define STATUSB_IP8 0 286 #define STATUSF_IP8 (_ULCAST_(1) << 0) 287 #define STATUSB_IP9 1 288 #define STATUSF_IP9 (_ULCAST_(1) << 1) 289 #define STATUSB_IP10 2 290 #define STATUSF_IP10 (_ULCAST_(1) << 2) 291 #define STATUSB_IP11 3 292 #define STATUSF_IP11 (_ULCAST_(1) << 3) 293 #define STATUSB_IP12 4 294 #define STATUSF_IP12 (_ULCAST_(1) << 4) 295 #define STATUSB_IP13 5 296 #define STATUSF_IP13 (_ULCAST_(1) << 5) 297 #define STATUSB_IP14 6 298 #define STATUSF_IP14 (_ULCAST_(1) << 6) 299 #define STATUSB_IP15 7 300 #define STATUSF_IP15 (_ULCAST_(1) << 7) 301 #define ST0_CH 0x00040000 302 #define ST0_NMI 0x00080000 303 #define ST0_SR 0x00100000 304 #define ST0_TS 0x00200000 305 #define ST0_BEV 0x00400000 306 #define ST0_RE 0x02000000 307 #define ST0_FR 0x04000000 308 #define ST0_CU 0xf0000000 309 #define ST0_CU0 0x10000000 310 #define ST0_CU1 0x20000000 311 #define ST0_CU2 0x40000000 312 #define ST0_CU3 0x80000000 313 #define ST0_XX 0x80000000 /* MIPS IV naming */ 314 315 /* 316 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 317 */ 318 #define INTCTLB_IPFDC 23 319 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) 320 #define INTCTLB_IPPCI 26 321 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 322 #define INTCTLB_IPTI 29 323 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 324 325 /* 326 * Bitfields and bit numbers in the coprocessor 0 cause register. 327 * 328 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 329 */ 330 #define CAUSEB_EXCCODE 2 331 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 332 #define CAUSEB_IP 8 333 #define CAUSEF_IP (_ULCAST_(255) << 8) 334 #define CAUSEB_IP0 8 335 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 336 #define CAUSEB_IP1 9 337 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 338 #define CAUSEB_IP2 10 339 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 340 #define CAUSEB_IP3 11 341 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 342 #define CAUSEB_IP4 12 343 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 344 #define CAUSEB_IP5 13 345 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 346 #define CAUSEB_IP6 14 347 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 348 #define CAUSEB_IP7 15 349 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 350 #define CAUSEB_FDCI 21 351 #define CAUSEF_FDCI (_ULCAST_(1) << 21) 352 #define CAUSEB_IV 23 353 #define CAUSEF_IV (_ULCAST_(1) << 23) 354 #define CAUSEB_PCI 26 355 #define CAUSEF_PCI (_ULCAST_(1) << 26) 356 #define CAUSEB_CE 28 357 #define CAUSEF_CE (_ULCAST_(3) << 28) 358 #define CAUSEB_TI 30 359 #define CAUSEF_TI (_ULCAST_(1) << 30) 360 #define CAUSEB_BD 31 361 #define CAUSEF_BD (_ULCAST_(1) << 31) 362 363 /* 364 * Bits in the coprocessor 0 config register. 365 */ 366 /* Generic bits. */ 367 #define CONF_CM_CACHABLE_NO_WA 0 368 #define CONF_CM_CACHABLE_WA 1 369 #define CONF_CM_UNCACHED 2 370 #define CONF_CM_CACHABLE_NONCOHERENT 3 371 #define CONF_CM_CACHABLE_CE 4 372 #define CONF_CM_CACHABLE_COW 5 373 #define CONF_CM_CACHABLE_CUW 6 374 #define CONF_CM_CACHABLE_ACCELERATED 7 375 #define CONF_CM_CMASK 7 376 #define CONF_BE (_ULCAST_(1) << 15) 377 378 /* Bits common to various processors. */ 379 #define CONF_CU (_ULCAST_(1) << 3) 380 #define CONF_DB (_ULCAST_(1) << 4) 381 #define CONF_IB (_ULCAST_(1) << 5) 382 #define CONF_DC (_ULCAST_(7) << 6) 383 #define CONF_IC (_ULCAST_(7) << 9) 384 #define CONF_EB (_ULCAST_(1) << 13) 385 #define CONF_EM (_ULCAST_(1) << 14) 386 #define CONF_SM (_ULCAST_(1) << 16) 387 #define CONF_SC (_ULCAST_(1) << 17) 388 #define CONF_EW (_ULCAST_(3) << 18) 389 #define CONF_EP (_ULCAST_(15) << 24) 390 #define CONF_EC (_ULCAST_(7) << 28) 391 #define CONF_CM (_ULCAST_(1) << 31) 392 393 /* Bits specific to the R4xx0. */ 394 #define R4K_CONF_SW (_ULCAST_(1) << 20) 395 #define R4K_CONF_SS (_ULCAST_(1) << 21) 396 #define R4K_CONF_SB (_ULCAST_(3) << 22) 397 398 /* Bits specific to the R5000. */ 399 #define R5K_CONF_SE (_ULCAST_(1) << 12) 400 #define R5K_CONF_SS (_ULCAST_(3) << 20) 401 402 /* Bits specific to the RM7000. */ 403 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 404 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 405 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 406 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 407 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 408 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 409 410 /* Bits specific to the R10000. */ 411 #define R10K_CONF_DN (_ULCAST_(3) << 3) 412 #define R10K_CONF_CT (_ULCAST_(1) << 5) 413 #define R10K_CONF_PE (_ULCAST_(1) << 6) 414 #define R10K_CONF_PM (_ULCAST_(3) << 7) 415 #define R10K_CONF_EC (_ULCAST_(15) << 9) 416 #define R10K_CONF_SB (_ULCAST_(1) << 13) 417 #define R10K_CONF_SK (_ULCAST_(1) << 14) 418 #define R10K_CONF_SS (_ULCAST_(7) << 16) 419 #define R10K_CONF_SC (_ULCAST_(7) << 19) 420 #define R10K_CONF_DC (_ULCAST_(7) << 26) 421 #define R10K_CONF_IC (_ULCAST_(7) << 29) 422 423 /* Bits specific to the VR41xx. */ 424 #define VR41_CONF_CS (_ULCAST_(1) << 12) 425 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 426 #define VR41_CONF_BP (_ULCAST_(1) << 16) 427 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 428 #define VR41_CONF_AD (_ULCAST_(1) << 23) 429 430 /* Bits specific to the R30xx. */ 431 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 432 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 433 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 434 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 435 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 436 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 437 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 438 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 439 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 440 441 /* Bits specific to the TX49. */ 442 #define TX49_CONF_DC (_ULCAST_(1) << 16) 443 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 444 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 445 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 446 447 /* Bits specific to the MIPS32/64 PRA. */ 448 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 449 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) 450 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) 451 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 452 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 453 #define MIPS_CONF_M (_ULCAST_(1) << 31) 454 455 /* 456 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 457 */ 458 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 459 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 460 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 461 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 462 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 463 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 464 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 465 #define MIPS_CONF1_DA_SHF 7 466 #define MIPS_CONF1_DA_SZ 3 467 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 468 #define MIPS_CONF1_DL_SHF 10 469 #define MIPS_CONF1_DL_SZ 3 470 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 471 #define MIPS_CONF1_DS_SHF 13 472 #define MIPS_CONF1_DS_SZ 3 473 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 474 #define MIPS_CONF1_IA_SHF 16 475 #define MIPS_CONF1_IA_SZ 3 476 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 477 #define MIPS_CONF1_IL_SHF 19 478 #define MIPS_CONF1_IL_SZ 3 479 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 480 #define MIPS_CONF1_IS_SHF 22 481 #define MIPS_CONF1_IS_SZ 3 482 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 483 #define MIPS_CONF1_TLBS_SHIFT (25) 484 #define MIPS_CONF1_TLBS_SIZE (6) 485 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 486 487 #define MIPS_CONF2_SA (_ULCAST_(15) << 0) 488 #define MIPS_CONF2_SL (_ULCAST_(15) << 4) 489 #define MIPS_CONF2_SS (_ULCAST_(15) << 8) 490 #define MIPS_CONF2_SU (_ULCAST_(15) << 12) 491 #define MIPS_CONF2_TA (_ULCAST_(15) << 16) 492 #define MIPS_CONF2_TL (_ULCAST_(15) << 20) 493 #define MIPS_CONF2_TS (_ULCAST_(15) << 24) 494 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 495 496 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 497 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 498 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 499 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 500 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 501 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 502 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 503 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 504 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 505 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 506 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 507 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 508 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 509 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 510 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 511 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 512 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 513 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 514 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 515 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 516 #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 517 #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 518 #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 519 #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 520 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 521 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 522 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 523 524 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 525 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 526 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 527 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 528 #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 529 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 530 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 531 /* bits 10:8 in FTLB-only configurations */ 532 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 533 /* bits 12:8 in VTLB-FTLB only configurations */ 534 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 535 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 536 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 537 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 538 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 539 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 540 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 541 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 542 #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 543 #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 544 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 545 546 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 547 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 548 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 549 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) 550 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) 551 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) 552 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) 553 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 554 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 555 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 556 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 557 558 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 559 /* proAptiv FTLB on/off bit */ 560 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 561 /* FTLB probability bits */ 562 #define MIPS_CONF6_FTLBP_SHIFT (16) 563 564 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 565 566 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 567 568 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 569 #define MIPS_CONF7_AR (_ULCAST_(1) << 16) 570 /* FTLB probability bits for R6 */ 571 #define MIPS_CONF7_FTLBP_SHIFT (18) 572 573 /* MAAR bit definitions */ 574 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) 575 #define MIPS_MAAR_ADDR_SHIFT 12 576 #define MIPS_MAAR_S (_ULCAST_(1) << 1) 577 #define MIPS_MAAR_V (_ULCAST_(1) << 0) 578 579 /* CMGCRBase bit definitions */ 580 #define MIPS_CMGCRB_BASE 11 581 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 582 583 /* 584 * Bits in the MIPS32 Memory Segmentation registers. 585 */ 586 #define MIPS_SEGCFG_PA_SHIFT 9 587 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 588 #define MIPS_SEGCFG_AM_SHIFT 4 589 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 590 #define MIPS_SEGCFG_EU_SHIFT 3 591 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 592 #define MIPS_SEGCFG_C_SHIFT 0 593 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 594 595 #define MIPS_SEGCFG_UUSK _ULCAST_(7) 596 #define MIPS_SEGCFG_USK _ULCAST_(5) 597 #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 598 #define MIPS_SEGCFG_MUSK _ULCAST_(3) 599 #define MIPS_SEGCFG_MSK _ULCAST_(2) 600 #define MIPS_SEGCFG_MK _ULCAST_(1) 601 #define MIPS_SEGCFG_UK _ULCAST_(0) 602 603 #define MIPS_PWFIELD_GDI_SHIFT 24 604 #define MIPS_PWFIELD_GDI_MASK 0x3f000000 605 #define MIPS_PWFIELD_UDI_SHIFT 18 606 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 607 #define MIPS_PWFIELD_MDI_SHIFT 12 608 #define MIPS_PWFIELD_MDI_MASK 0x0003f000 609 #define MIPS_PWFIELD_PTI_SHIFT 6 610 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 611 #define MIPS_PWFIELD_PTEI_SHIFT 0 612 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f 613 614 #define MIPS_PWSIZE_GDW_SHIFT 24 615 #define MIPS_PWSIZE_GDW_MASK 0x3f000000 616 #define MIPS_PWSIZE_UDW_SHIFT 18 617 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 618 #define MIPS_PWSIZE_MDW_SHIFT 12 619 #define MIPS_PWSIZE_MDW_MASK 0x0003f000 620 #define MIPS_PWSIZE_PTW_SHIFT 6 621 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 622 #define MIPS_PWSIZE_PTEW_SHIFT 0 623 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f 624 625 #define MIPS_PWCTL_PWEN_SHIFT 31 626 #define MIPS_PWCTL_PWEN_MASK 0x80000000 627 #define MIPS_PWCTL_DPH_SHIFT 7 628 #define MIPS_PWCTL_DPH_MASK 0x00000080 629 #define MIPS_PWCTL_HUGEPG_SHIFT 6 630 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 631 #define MIPS_PWCTL_PSN_SHIFT 0 632 #define MIPS_PWCTL_PSN_MASK 0x0000003f 633 634 /* CDMMBase register bit definitions */ 635 #define MIPS_CDMMBASE_SIZE_SHIFT 0 636 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) 637 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) 638 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) 639 #define MIPS_CDMMBASE_ADDR_SHIFT 11 640 #define MIPS_CDMMBASE_ADDR_START 15 641 642 /* 643 * Bitfields in the TX39 family CP0 Configuration Register 3 644 */ 645 #define TX39_CONF_ICS_SHIFT 19 646 #define TX39_CONF_ICS_MASK 0x00380000 647 #define TX39_CONF_ICS_1KB 0x00000000 648 #define TX39_CONF_ICS_2KB 0x00080000 649 #define TX39_CONF_ICS_4KB 0x00100000 650 #define TX39_CONF_ICS_8KB 0x00180000 651 #define TX39_CONF_ICS_16KB 0x00200000 652 653 #define TX39_CONF_DCS_SHIFT 16 654 #define TX39_CONF_DCS_MASK 0x00070000 655 #define TX39_CONF_DCS_1KB 0x00000000 656 #define TX39_CONF_DCS_2KB 0x00010000 657 #define TX39_CONF_DCS_4KB 0x00020000 658 #define TX39_CONF_DCS_8KB 0x00030000 659 #define TX39_CONF_DCS_16KB 0x00040000 660 661 #define TX39_CONF_CWFON 0x00004000 662 #define TX39_CONF_WBON 0x00002000 663 #define TX39_CONF_RF_SHIFT 10 664 #define TX39_CONF_RF_MASK 0x00000c00 665 #define TX39_CONF_DOZE 0x00000200 666 #define TX39_CONF_HALT 0x00000100 667 #define TX39_CONF_LOCK 0x00000080 668 #define TX39_CONF_ICE 0x00000020 669 #define TX39_CONF_DCE 0x00000010 670 #define TX39_CONF_IRSIZE_SHIFT 2 671 #define TX39_CONF_IRSIZE_MASK 0x0000000c 672 #define TX39_CONF_DRSIZE_SHIFT 0 673 #define TX39_CONF_DRSIZE_MASK 0x00000003 674 675 /* 676 * Interesting Bits in the R10K CP0 Branch Diagnostic Register 677 */ 678 /* Disable Branch Target Address Cache */ 679 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) 680 /* Enable Branch Prediction Global History */ 681 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) 682 /* Disable Branch Return Cache */ 683 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) 684 685 /* 686 * Coprocessor 1 (FPU) register names 687 */ 688 #define CP1_REVISION $0 689 #define CP1_UFR $1 690 #define CP1_UNFR $4 691 #define CP1_FCCR $25 692 #define CP1_FEXR $26 693 #define CP1_FENR $28 694 #define CP1_STATUS $31 695 696 697 /* 698 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 699 */ 700 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 701 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 702 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 703 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 704 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 705 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 706 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 707 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) 708 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) 709 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) 710 711 /* 712 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. 713 */ 714 #define MIPS_FCCR_CONDX_S 0 715 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) 716 #define MIPS_FCCR_COND0_S 0 717 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) 718 #define MIPS_FCCR_COND1_S 1 719 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) 720 #define MIPS_FCCR_COND2_S 2 721 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) 722 #define MIPS_FCCR_COND3_S 3 723 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) 724 #define MIPS_FCCR_COND4_S 4 725 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) 726 #define MIPS_FCCR_COND5_S 5 727 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) 728 #define MIPS_FCCR_COND6_S 6 729 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) 730 #define MIPS_FCCR_COND7_S 7 731 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) 732 733 /* 734 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. 735 */ 736 #define MIPS_FENR_FS_S 2 737 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) 738 739 /* 740 * FPU Status Register Values 741 */ 742 #define FPU_CSR_COND_S 23 /* $fcc0 */ 743 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) 744 745 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ 746 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) 747 748 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ 749 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) 750 #define FPU_CSR_COND1_S 25 /* $fcc1 */ 751 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) 752 #define FPU_CSR_COND2_S 26 /* $fcc2 */ 753 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) 754 #define FPU_CSR_COND3_S 27 /* $fcc3 */ 755 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) 756 #define FPU_CSR_COND4_S 28 /* $fcc4 */ 757 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) 758 #define FPU_CSR_COND5_S 29 /* $fcc5 */ 759 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) 760 #define FPU_CSR_COND6_S 30 /* $fcc6 */ 761 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) 762 #define FPU_CSR_COND7_S 31 /* $fcc7 */ 763 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) 764 765 /* 766 * Bits 22:20 of the FPU Status Register will be read as 0, 767 * and should be written as zero. 768 */ 769 #define FPU_CSR_RSVD (_ULCAST_(7) << 20) 770 771 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) 772 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) 773 774 /* 775 * X the exception cause indicator 776 * E the exception enable 777 * S the sticky/flag bit 778 */ 779 #define FPU_CSR_ALL_X 0x0003f000 780 #define FPU_CSR_UNI_X 0x00020000 781 #define FPU_CSR_INV_X 0x00010000 782 #define FPU_CSR_DIV_X 0x00008000 783 #define FPU_CSR_OVF_X 0x00004000 784 #define FPU_CSR_UDF_X 0x00002000 785 #define FPU_CSR_INE_X 0x00001000 786 787 #define FPU_CSR_ALL_E 0x00000f80 788 #define FPU_CSR_INV_E 0x00000800 789 #define FPU_CSR_DIV_E 0x00000400 790 #define FPU_CSR_OVF_E 0x00000200 791 #define FPU_CSR_UDF_E 0x00000100 792 #define FPU_CSR_INE_E 0x00000080 793 794 #define FPU_CSR_ALL_S 0x0000007c 795 #define FPU_CSR_INV_S 0x00000040 796 #define FPU_CSR_DIV_S 0x00000020 797 #define FPU_CSR_OVF_S 0x00000010 798 #define FPU_CSR_UDF_S 0x00000008 799 #define FPU_CSR_INE_S 0x00000004 800 801 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 802 #define FPU_CSR_RM 0x00000003 803 #define FPU_CSR_RN 0x0 /* nearest */ 804 #define FPU_CSR_RZ 0x1 /* towards zero */ 805 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 806 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 807 808 809 #ifndef __ASSEMBLY__ 810 811 /* 812 * Macros for handling the ISA mode bit for MIPS16 and microMIPS. 813 */ 814 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ 815 defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 816 #define get_isa16_mode(x) ((x) & 0x1) 817 #define msk_isa16_mode(x) ((x) & ~0x1) 818 #define set_isa16_mode(x) do { (x) |= 0x1; } while (0) 819 #else 820 #define get_isa16_mode(x) 0 821 #define msk_isa16_mode(x) (x) 822 #define set_isa16_mode(x) do { } while (0) 823 #endif 824 825 /* 826 * microMIPS instructions can be 16-bit or 32-bit in length. This 827 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 828 */ 829 static inline int mm_insn_16bit(u16 insn) 830 { 831 u16 opcode = (insn >> 10) & 0x7; 832 833 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 834 } 835 836 /* 837 * TLB Invalidate Flush 838 */ 839 static inline void tlbinvf(void) 840 { 841 __asm__ __volatile__( 842 ".set push\n\t" 843 ".set noreorder\n\t" 844 ".word 0x42000004\n\t" /* tlbinvf */ 845 ".set pop"); 846 } 847 848 849 /* 850 * Functions to access the R10000 performance counters. These are basically 851 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 852 * performance counter number encoded into bits 1 ... 5 of the instruction. 853 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 854 * disassembler these will look like an access to sel 0 or 1. 855 */ 856 #define read_r10k_perf_cntr(counter) \ 857 ({ \ 858 unsigned int __res; \ 859 __asm__ __volatile__( \ 860 "mfpc\t%0, %1" \ 861 : "=r" (__res) \ 862 : "i" (counter)); \ 863 \ 864 __res; \ 865 }) 866 867 #define write_r10k_perf_cntr(counter,val) \ 868 do { \ 869 __asm__ __volatile__( \ 870 "mtpc\t%0, %1" \ 871 : \ 872 : "r" (val), "i" (counter)); \ 873 } while (0) 874 875 #define read_r10k_perf_event(counter) \ 876 ({ \ 877 unsigned int __res; \ 878 __asm__ __volatile__( \ 879 "mfps\t%0, %1" \ 880 : "=r" (__res) \ 881 : "i" (counter)); \ 882 \ 883 __res; \ 884 }) 885 886 #define write_r10k_perf_cntl(counter,val) \ 887 do { \ 888 __asm__ __volatile__( \ 889 "mtps\t%0, %1" \ 890 : \ 891 : "r" (val), "i" (counter)); \ 892 } while (0) 893 894 895 /* 896 * Macros to access the system control coprocessor 897 */ 898 899 #define __read_32bit_c0_register(source, sel) \ 900 ({ unsigned int __res; \ 901 if (sel == 0) \ 902 __asm__ __volatile__( \ 903 "mfc0\t%0, " #source "\n\t" \ 904 : "=r" (__res)); \ 905 else \ 906 __asm__ __volatile__( \ 907 ".set\tmips32\n\t" \ 908 "mfc0\t%0, " #source ", " #sel "\n\t" \ 909 ".set\tmips0\n\t" \ 910 : "=r" (__res)); \ 911 __res; \ 912 }) 913 914 #define __read_64bit_c0_register(source, sel) \ 915 ({ unsigned long long __res; \ 916 if (sizeof(unsigned long) == 4) \ 917 __res = __read_64bit_c0_split(source, sel); \ 918 else if (sel == 0) \ 919 __asm__ __volatile__( \ 920 ".set\tmips3\n\t" \ 921 "dmfc0\t%0, " #source "\n\t" \ 922 ".set\tmips0" \ 923 : "=r" (__res)); \ 924 else \ 925 __asm__ __volatile__( \ 926 ".set\tmips64\n\t" \ 927 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 928 ".set\tmips0" \ 929 : "=r" (__res)); \ 930 __res; \ 931 }) 932 933 #define __write_32bit_c0_register(register, sel, value) \ 934 do { \ 935 if (sel == 0) \ 936 __asm__ __volatile__( \ 937 "mtc0\t%z0, " #register "\n\t" \ 938 : : "Jr" ((unsigned int)(value))); \ 939 else \ 940 __asm__ __volatile__( \ 941 ".set\tmips32\n\t" \ 942 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 943 ".set\tmips0" \ 944 : : "Jr" ((unsigned int)(value))); \ 945 } while (0) 946 947 #define __write_64bit_c0_register(register, sel, value) \ 948 do { \ 949 if (sizeof(unsigned long) == 4) \ 950 __write_64bit_c0_split(register, sel, value); \ 951 else if (sel == 0) \ 952 __asm__ __volatile__( \ 953 ".set\tmips3\n\t" \ 954 "dmtc0\t%z0, " #register "\n\t" \ 955 ".set\tmips0" \ 956 : : "Jr" (value)); \ 957 else \ 958 __asm__ __volatile__( \ 959 ".set\tmips64\n\t" \ 960 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 961 ".set\tmips0" \ 962 : : "Jr" (value)); \ 963 } while (0) 964 965 #define __read_ulong_c0_register(reg, sel) \ 966 ((sizeof(unsigned long) == 4) ? \ 967 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 968 (unsigned long) __read_64bit_c0_register(reg, sel)) 969 970 #define __write_ulong_c0_register(reg, sel, val) \ 971 do { \ 972 if (sizeof(unsigned long) == 4) \ 973 __write_32bit_c0_register(reg, sel, val); \ 974 else \ 975 __write_64bit_c0_register(reg, sel, val); \ 976 } while (0) 977 978 /* 979 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 980 */ 981 #define __read_32bit_c0_ctrl_register(source) \ 982 ({ unsigned int __res; \ 983 __asm__ __volatile__( \ 984 "cfc0\t%0, " #source "\n\t" \ 985 : "=r" (__res)); \ 986 __res; \ 987 }) 988 989 #define __write_32bit_c0_ctrl_register(register, value) \ 990 do { \ 991 __asm__ __volatile__( \ 992 "ctc0\t%z0, " #register "\n\t" \ 993 : : "Jr" ((unsigned int)(value))); \ 994 } while (0) 995 996 /* 997 * These versions are only needed for systems with more than 38 bits of 998 * physical address space running the 32-bit kernel. That's none atm :-) 999 */ 1000 #define __read_64bit_c0_split(source, sel) \ 1001 ({ \ 1002 unsigned long long __val; \ 1003 unsigned long __flags; \ 1004 \ 1005 local_irq_save(__flags); \ 1006 if (sel == 0) \ 1007 __asm__ __volatile__( \ 1008 ".set\tmips64\n\t" \ 1009 "dmfc0\t%M0, " #source "\n\t" \ 1010 "dsll\t%L0, %M0, 32\n\t" \ 1011 "dsra\t%M0, %M0, 32\n\t" \ 1012 "dsra\t%L0, %L0, 32\n\t" \ 1013 ".set\tmips0" \ 1014 : "=r" (__val)); \ 1015 else \ 1016 __asm__ __volatile__( \ 1017 ".set\tmips64\n\t" \ 1018 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 1019 "dsll\t%L0, %M0, 32\n\t" \ 1020 "dsra\t%M0, %M0, 32\n\t" \ 1021 "dsra\t%L0, %L0, 32\n\t" \ 1022 ".set\tmips0" \ 1023 : "=r" (__val)); \ 1024 local_irq_restore(__flags); \ 1025 \ 1026 __val; \ 1027 }) 1028 1029 #define __write_64bit_c0_split(source, sel, val) \ 1030 do { \ 1031 unsigned long __flags; \ 1032 \ 1033 local_irq_save(__flags); \ 1034 if (sel == 0) \ 1035 __asm__ __volatile__( \ 1036 ".set\tmips64\n\t" \ 1037 "dsll\t%L0, %L0, 32\n\t" \ 1038 "dsrl\t%L0, %L0, 32\n\t" \ 1039 "dsll\t%M0, %M0, 32\n\t" \ 1040 "or\t%L0, %L0, %M0\n\t" \ 1041 "dmtc0\t%L0, " #source "\n\t" \ 1042 ".set\tmips0" \ 1043 : : "r" (val)); \ 1044 else \ 1045 __asm__ __volatile__( \ 1046 ".set\tmips64\n\t" \ 1047 "dsll\t%L0, %L0, 32\n\t" \ 1048 "dsrl\t%L0, %L0, 32\n\t" \ 1049 "dsll\t%M0, %M0, 32\n\t" \ 1050 "or\t%L0, %L0, %M0\n\t" \ 1051 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 1052 ".set\tmips0" \ 1053 : : "r" (val)); \ 1054 local_irq_restore(__flags); \ 1055 } while (0) 1056 1057 #define __readx_32bit_c0_register(source) \ 1058 ({ \ 1059 unsigned int __res; \ 1060 \ 1061 __asm__ __volatile__( \ 1062 " .set push \n" \ 1063 " .set noat \n" \ 1064 " .set mips32r2 \n" \ 1065 " .insn \n" \ 1066 " # mfhc0 $1, %1 \n" \ 1067 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ 1068 " move %0, $1 \n" \ 1069 " .set pop \n" \ 1070 : "=r" (__res) \ 1071 : "i" (source)); \ 1072 __res; \ 1073 }) 1074 1075 #define __writex_32bit_c0_register(register, value) \ 1076 ({ \ 1077 __asm__ __volatile__( \ 1078 " .set push \n" \ 1079 " .set noat \n" \ 1080 " .set mips32r2 \n" \ 1081 " move $1, %0 \n" \ 1082 " # mthc0 $1, %1 \n" \ 1083 " .insn \n" \ 1084 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ 1085 " .set pop \n" \ 1086 : \ 1087 : "r" (value), "i" (register)); \ 1088 }) 1089 1090 #define read_c0_index() __read_32bit_c0_register($0, 0) 1091 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 1092 1093 #define read_c0_random() __read_32bit_c0_register($1, 0) 1094 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 1095 1096 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 1097 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 1098 1099 #define readx_c0_entrylo0() __readx_32bit_c0_register(2) 1100 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) 1101 1102 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 1103 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 1104 1105 #define readx_c0_entrylo1() __readx_32bit_c0_register(3) 1106 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) 1107 1108 #define read_c0_conf() __read_32bit_c0_register($3, 0) 1109 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 1110 1111 #define read_c0_context() __read_ulong_c0_register($4, 0) 1112 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 1113 1114 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 1115 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 1116 1117 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 1118 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 1119 1120 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 1121 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 1122 1123 #define read_c0_wired() __read_32bit_c0_register($6, 0) 1124 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 1125 1126 #define read_c0_info() __read_32bit_c0_register($7, 0) 1127 1128 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 1129 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 1130 1131 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 1132 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 1133 1134 #define read_c0_count() __read_32bit_c0_register($9, 0) 1135 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 1136 1137 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 1138 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 1139 1140 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 1141 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 1142 1143 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 1144 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 1145 1146 #define read_c0_compare() __read_32bit_c0_register($11, 0) 1147 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1148 1149 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1150 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1151 1152 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1153 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1154 1155 #define read_c0_status() __read_32bit_c0_register($12, 0) 1156 1157 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1158 1159 #define read_c0_cause() __read_32bit_c0_register($13, 0) 1160 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1161 1162 #define read_c0_epc() __read_ulong_c0_register($14, 0) 1163 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1164 1165 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1166 1167 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1168 1169 #define read_c0_config() __read_32bit_c0_register($16, 0) 1170 #define read_c0_config1() __read_32bit_c0_register($16, 1) 1171 #define read_c0_config2() __read_32bit_c0_register($16, 2) 1172 #define read_c0_config3() __read_32bit_c0_register($16, 3) 1173 #define read_c0_config4() __read_32bit_c0_register($16, 4) 1174 #define read_c0_config5() __read_32bit_c0_register($16, 5) 1175 #define read_c0_config6() __read_32bit_c0_register($16, 6) 1176 #define read_c0_config7() __read_32bit_c0_register($16, 7) 1177 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1178 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1179 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1180 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1181 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1182 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1183 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1184 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1185 1186 #define read_c0_lladdr() __read_ulong_c0_register($17, 0) 1187 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) 1188 #define read_c0_maar() __read_ulong_c0_register($17, 1) 1189 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) 1190 #define read_c0_maari() __read_32bit_c0_register($17, 2) 1191 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) 1192 1193 /* 1194 * The WatchLo register. There may be up to 8 of them. 1195 */ 1196 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1197 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1198 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1199 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1200 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1201 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1202 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1203 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1204 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1205 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1206 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1207 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1208 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1209 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1210 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1211 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1212 1213 /* 1214 * The WatchHi register. There may be up to 8 of them. 1215 */ 1216 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1217 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1218 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1219 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1220 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1221 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1222 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1223 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1224 1225 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1226 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1227 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1228 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1229 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1230 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1231 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1232 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1233 1234 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1235 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1236 1237 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1238 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1239 1240 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1241 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1242 1243 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1244 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1245 1246 /* R10K CP0 Branch Diagnostic register is 64bits wide */ 1247 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) 1248 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) 1249 1250 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1251 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1252 1253 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1254 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1255 1256 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1257 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1258 1259 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1260 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1261 1262 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1263 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1264 1265 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1266 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1267 1268 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1269 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1270 1271 /* 1272 * MIPS32 / MIPS64 performance counters 1273 */ 1274 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1275 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1276 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1277 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1278 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1279 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1280 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1281 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1282 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1283 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1284 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1285 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1286 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1287 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1288 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1289 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1290 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1291 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1292 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1293 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1294 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1295 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1296 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1297 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1298 1299 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1300 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1301 1302 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1303 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1304 1305 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1306 1307 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1308 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1309 1310 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1311 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1312 1313 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1314 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1315 1316 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1317 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1318 1319 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1320 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1321 1322 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1323 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1324 1325 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1326 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1327 1328 /* MIPSR2 */ 1329 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1330 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1331 1332 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1333 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1334 1335 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1336 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1337 1338 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1339 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1340 1341 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1342 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1343 1344 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) 1345 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) 1346 1347 /* MIPSR3 */ 1348 #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1349 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1350 1351 #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1352 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1353 1354 #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1355 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1356 1357 /* Hardware Page Table Walker */ 1358 #define read_c0_pwbase() __read_ulong_c0_register($5, 5) 1359 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) 1360 1361 #define read_c0_pwfield() __read_ulong_c0_register($5, 6) 1362 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) 1363 1364 #define read_c0_pwsize() __read_ulong_c0_register($5, 7) 1365 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) 1366 1367 #define read_c0_pwctl() __read_32bit_c0_register($6, 6) 1368 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) 1369 1370 /* Cavium OCTEON (cnMIPS) */ 1371 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1372 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1373 1374 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1375 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1376 1377 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1378 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1379 /* 1380 * The cacheerr registers are not standardized. On OCTEON, they are 1381 * 64 bits wide. 1382 */ 1383 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1384 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1385 1386 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1387 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1388 1389 /* BMIPS3300 */ 1390 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1391 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1392 1393 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1394 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1395 1396 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1397 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1398 1399 /* BMIPS43xx */ 1400 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1401 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1402 1403 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1404 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1405 1406 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1407 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1408 1409 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1410 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1411 1412 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1413 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1414 1415 /* BMIPS5000 */ 1416 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1417 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1418 1419 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1420 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1421 1422 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1423 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1424 1425 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1426 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1427 1428 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1429 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1430 1431 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1432 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1433 1434 /* 1435 * Macros to access the floating point coprocessor control registers 1436 */ 1437 #define _read_32bit_cp1_register(source, gas_hardfloat) \ 1438 ({ \ 1439 unsigned int __res; \ 1440 \ 1441 __asm__ __volatile__( \ 1442 " .set push \n" \ 1443 " .set reorder \n" \ 1444 " # gas fails to assemble cfc1 for some archs, \n" \ 1445 " # like Octeon. \n" \ 1446 " .set mips1 \n" \ 1447 " "STR(gas_hardfloat)" \n" \ 1448 " cfc1 %0,"STR(source)" \n" \ 1449 " .set pop \n" \ 1450 : "=r" (__res)); \ 1451 __res; \ 1452 }) 1453 1454 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ 1455 ({ \ 1456 __asm__ __volatile__( \ 1457 " .set push \n" \ 1458 " .set reorder \n" \ 1459 " "STR(gas_hardfloat)" \n" \ 1460 " ctc1 %0,"STR(dest)" \n" \ 1461 " .set pop \n" \ 1462 : : "r" (val)); \ 1463 }) 1464 1465 #ifdef GAS_HAS_SET_HARDFLOAT 1466 #define read_32bit_cp1_register(source) \ 1467 _read_32bit_cp1_register(source, .set hardfloat) 1468 #define write_32bit_cp1_register(dest, val) \ 1469 _write_32bit_cp1_register(dest, val, .set hardfloat) 1470 #else 1471 #define read_32bit_cp1_register(source) \ 1472 _read_32bit_cp1_register(source, ) 1473 #define write_32bit_cp1_register(dest, val) \ 1474 _write_32bit_cp1_register(dest, val, ) 1475 #endif 1476 1477 #ifdef HAVE_AS_DSP 1478 #define rddsp(mask) \ 1479 ({ \ 1480 unsigned int __dspctl; \ 1481 \ 1482 __asm__ __volatile__( \ 1483 " .set push \n" \ 1484 " .set dsp \n" \ 1485 " rddsp %0, %x1 \n" \ 1486 " .set pop \n" \ 1487 : "=r" (__dspctl) \ 1488 : "i" (mask)); \ 1489 __dspctl; \ 1490 }) 1491 1492 #define wrdsp(val, mask) \ 1493 ({ \ 1494 __asm__ __volatile__( \ 1495 " .set push \n" \ 1496 " .set dsp \n" \ 1497 " wrdsp %0, %x1 \n" \ 1498 " .set pop \n" \ 1499 : \ 1500 : "r" (val), "i" (mask)); \ 1501 }) 1502 1503 #define mflo0() \ 1504 ({ \ 1505 long mflo0; \ 1506 __asm__( \ 1507 " .set push \n" \ 1508 " .set dsp \n" \ 1509 " mflo %0, $ac0 \n" \ 1510 " .set pop \n" \ 1511 : "=r" (mflo0)); \ 1512 mflo0; \ 1513 }) 1514 1515 #define mflo1() \ 1516 ({ \ 1517 long mflo1; \ 1518 __asm__( \ 1519 " .set push \n" \ 1520 " .set dsp \n" \ 1521 " mflo %0, $ac1 \n" \ 1522 " .set pop \n" \ 1523 : "=r" (mflo1)); \ 1524 mflo1; \ 1525 }) 1526 1527 #define mflo2() \ 1528 ({ \ 1529 long mflo2; \ 1530 __asm__( \ 1531 " .set push \n" \ 1532 " .set dsp \n" \ 1533 " mflo %0, $ac2 \n" \ 1534 " .set pop \n" \ 1535 : "=r" (mflo2)); \ 1536 mflo2; \ 1537 }) 1538 1539 #define mflo3() \ 1540 ({ \ 1541 long mflo3; \ 1542 __asm__( \ 1543 " .set push \n" \ 1544 " .set dsp \n" \ 1545 " mflo %0, $ac3 \n" \ 1546 " .set pop \n" \ 1547 : "=r" (mflo3)); \ 1548 mflo3; \ 1549 }) 1550 1551 #define mfhi0() \ 1552 ({ \ 1553 long mfhi0; \ 1554 __asm__( \ 1555 " .set push \n" \ 1556 " .set dsp \n" \ 1557 " mfhi %0, $ac0 \n" \ 1558 " .set pop \n" \ 1559 : "=r" (mfhi0)); \ 1560 mfhi0; \ 1561 }) 1562 1563 #define mfhi1() \ 1564 ({ \ 1565 long mfhi1; \ 1566 __asm__( \ 1567 " .set push \n" \ 1568 " .set dsp \n" \ 1569 " mfhi %0, $ac1 \n" \ 1570 " .set pop \n" \ 1571 : "=r" (mfhi1)); \ 1572 mfhi1; \ 1573 }) 1574 1575 #define mfhi2() \ 1576 ({ \ 1577 long mfhi2; \ 1578 __asm__( \ 1579 " .set push \n" \ 1580 " .set dsp \n" \ 1581 " mfhi %0, $ac2 \n" \ 1582 " .set pop \n" \ 1583 : "=r" (mfhi2)); \ 1584 mfhi2; \ 1585 }) 1586 1587 #define mfhi3() \ 1588 ({ \ 1589 long mfhi3; \ 1590 __asm__( \ 1591 " .set push \n" \ 1592 " .set dsp \n" \ 1593 " mfhi %0, $ac3 \n" \ 1594 " .set pop \n" \ 1595 : "=r" (mfhi3)); \ 1596 mfhi3; \ 1597 }) 1598 1599 1600 #define mtlo0(x) \ 1601 ({ \ 1602 __asm__( \ 1603 " .set push \n" \ 1604 " .set dsp \n" \ 1605 " mtlo %0, $ac0 \n" \ 1606 " .set pop \n" \ 1607 : \ 1608 : "r" (x)); \ 1609 }) 1610 1611 #define mtlo1(x) \ 1612 ({ \ 1613 __asm__( \ 1614 " .set push \n" \ 1615 " .set dsp \n" \ 1616 " mtlo %0, $ac1 \n" \ 1617 " .set pop \n" \ 1618 : \ 1619 : "r" (x)); \ 1620 }) 1621 1622 #define mtlo2(x) \ 1623 ({ \ 1624 __asm__( \ 1625 " .set push \n" \ 1626 " .set dsp \n" \ 1627 " mtlo %0, $ac2 \n" \ 1628 " .set pop \n" \ 1629 : \ 1630 : "r" (x)); \ 1631 }) 1632 1633 #define mtlo3(x) \ 1634 ({ \ 1635 __asm__( \ 1636 " .set push \n" \ 1637 " .set dsp \n" \ 1638 " mtlo %0, $ac3 \n" \ 1639 " .set pop \n" \ 1640 : \ 1641 : "r" (x)); \ 1642 }) 1643 1644 #define mthi0(x) \ 1645 ({ \ 1646 __asm__( \ 1647 " .set push \n" \ 1648 " .set dsp \n" \ 1649 " mthi %0, $ac0 \n" \ 1650 " .set pop \n" \ 1651 : \ 1652 : "r" (x)); \ 1653 }) 1654 1655 #define mthi1(x) \ 1656 ({ \ 1657 __asm__( \ 1658 " .set push \n" \ 1659 " .set dsp \n" \ 1660 " mthi %0, $ac1 \n" \ 1661 " .set pop \n" \ 1662 : \ 1663 : "r" (x)); \ 1664 }) 1665 1666 #define mthi2(x) \ 1667 ({ \ 1668 __asm__( \ 1669 " .set push \n" \ 1670 " .set dsp \n" \ 1671 " mthi %0, $ac2 \n" \ 1672 " .set pop \n" \ 1673 : \ 1674 : "r" (x)); \ 1675 }) 1676 1677 #define mthi3(x) \ 1678 ({ \ 1679 __asm__( \ 1680 " .set push \n" \ 1681 " .set dsp \n" \ 1682 " mthi %0, $ac3 \n" \ 1683 " .set pop \n" \ 1684 : \ 1685 : "r" (x)); \ 1686 }) 1687 1688 #else 1689 1690 #ifdef CONFIG_CPU_MICROMIPS 1691 #define rddsp(mask) \ 1692 ({ \ 1693 unsigned int __res; \ 1694 \ 1695 __asm__ __volatile__( \ 1696 " .set push \n" \ 1697 " .set noat \n" \ 1698 " # rddsp $1, %x1 \n" \ 1699 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1700 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1701 " move %0, $1 \n" \ 1702 " .set pop \n" \ 1703 : "=r" (__res) \ 1704 : "i" (mask)); \ 1705 __res; \ 1706 }) 1707 1708 #define wrdsp(val, mask) \ 1709 ({ \ 1710 __asm__ __volatile__( \ 1711 " .set push \n" \ 1712 " .set noat \n" \ 1713 " move $1, %0 \n" \ 1714 " # wrdsp $1, %x1 \n" \ 1715 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1716 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1717 " .set pop \n" \ 1718 : \ 1719 : "r" (val), "i" (mask)); \ 1720 }) 1721 1722 #define _umips_dsp_mfxxx(ins) \ 1723 ({ \ 1724 unsigned long __treg; \ 1725 \ 1726 __asm__ __volatile__( \ 1727 " .set push \n" \ 1728 " .set noat \n" \ 1729 " .hword 0x0001 \n" \ 1730 " .hword %x1 \n" \ 1731 " move %0, $1 \n" \ 1732 " .set pop \n" \ 1733 : "=r" (__treg) \ 1734 : "i" (ins)); \ 1735 __treg; \ 1736 }) 1737 1738 #define _umips_dsp_mtxxx(val, ins) \ 1739 ({ \ 1740 __asm__ __volatile__( \ 1741 " .set push \n" \ 1742 " .set noat \n" \ 1743 " move $1, %0 \n" \ 1744 " .hword 0x0001 \n" \ 1745 " .hword %x1 \n" \ 1746 " .set pop \n" \ 1747 : \ 1748 : "r" (val), "i" (ins)); \ 1749 }) 1750 1751 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1752 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1753 1754 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1755 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1756 1757 #define mflo0() _umips_dsp_mflo(0) 1758 #define mflo1() _umips_dsp_mflo(1) 1759 #define mflo2() _umips_dsp_mflo(2) 1760 #define mflo3() _umips_dsp_mflo(3) 1761 1762 #define mfhi0() _umips_dsp_mfhi(0) 1763 #define mfhi1() _umips_dsp_mfhi(1) 1764 #define mfhi2() _umips_dsp_mfhi(2) 1765 #define mfhi3() _umips_dsp_mfhi(3) 1766 1767 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1768 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1769 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1770 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1771 1772 #define mthi0(x) _umips_dsp_mthi(x, 0) 1773 #define mthi1(x) _umips_dsp_mthi(x, 1) 1774 #define mthi2(x) _umips_dsp_mthi(x, 2) 1775 #define mthi3(x) _umips_dsp_mthi(x, 3) 1776 1777 #else /* !CONFIG_CPU_MICROMIPS */ 1778 #define rddsp(mask) \ 1779 ({ \ 1780 unsigned int __res; \ 1781 \ 1782 __asm__ __volatile__( \ 1783 " .set push \n" \ 1784 " .set noat \n" \ 1785 " # rddsp $1, %x1 \n" \ 1786 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1787 " move %0, $1 \n" \ 1788 " .set pop \n" \ 1789 : "=r" (__res) \ 1790 : "i" (mask)); \ 1791 __res; \ 1792 }) 1793 1794 #define wrdsp(val, mask) \ 1795 ({ \ 1796 __asm__ __volatile__( \ 1797 " .set push \n" \ 1798 " .set noat \n" \ 1799 " move $1, %0 \n" \ 1800 " # wrdsp $1, %x1 \n" \ 1801 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1802 " .set pop \n" \ 1803 : \ 1804 : "r" (val), "i" (mask)); \ 1805 }) 1806 1807 #define _dsp_mfxxx(ins) \ 1808 ({ \ 1809 unsigned long __treg; \ 1810 \ 1811 __asm__ __volatile__( \ 1812 " .set push \n" \ 1813 " .set noat \n" \ 1814 " .word (0x00000810 | %1) \n" \ 1815 " move %0, $1 \n" \ 1816 " .set pop \n" \ 1817 : "=r" (__treg) \ 1818 : "i" (ins)); \ 1819 __treg; \ 1820 }) 1821 1822 #define _dsp_mtxxx(val, ins) \ 1823 ({ \ 1824 __asm__ __volatile__( \ 1825 " .set push \n" \ 1826 " .set noat \n" \ 1827 " move $1, %0 \n" \ 1828 " .word (0x00200011 | %1) \n" \ 1829 " .set pop \n" \ 1830 : \ 1831 : "r" (val), "i" (ins)); \ 1832 }) 1833 1834 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1835 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1836 1837 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1838 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1839 1840 #define mflo0() _dsp_mflo(0) 1841 #define mflo1() _dsp_mflo(1) 1842 #define mflo2() _dsp_mflo(2) 1843 #define mflo3() _dsp_mflo(3) 1844 1845 #define mfhi0() _dsp_mfhi(0) 1846 #define mfhi1() _dsp_mfhi(1) 1847 #define mfhi2() _dsp_mfhi(2) 1848 #define mfhi3() _dsp_mfhi(3) 1849 1850 #define mtlo0(x) _dsp_mtlo(x, 0) 1851 #define mtlo1(x) _dsp_mtlo(x, 1) 1852 #define mtlo2(x) _dsp_mtlo(x, 2) 1853 #define mtlo3(x) _dsp_mtlo(x, 3) 1854 1855 #define mthi0(x) _dsp_mthi(x, 0) 1856 #define mthi1(x) _dsp_mthi(x, 1) 1857 #define mthi2(x) _dsp_mthi(x, 2) 1858 #define mthi3(x) _dsp_mthi(x, 3) 1859 1860 #endif /* CONFIG_CPU_MICROMIPS */ 1861 #endif 1862 1863 /* 1864 * TLB operations. 1865 * 1866 * It is responsibility of the caller to take care of any TLB hazards. 1867 */ 1868 static inline void tlb_probe(void) 1869 { 1870 __asm__ __volatile__( 1871 ".set noreorder\n\t" 1872 "tlbp\n\t" 1873 ".set reorder"); 1874 } 1875 1876 static inline void tlb_read(void) 1877 { 1878 #if MIPS34K_MISSED_ITLB_WAR 1879 int res = 0; 1880 1881 __asm__ __volatile__( 1882 " .set push \n" 1883 " .set noreorder \n" 1884 " .set noat \n" 1885 " .set mips32r2 \n" 1886 " .word 0x41610001 # dvpe $1 \n" 1887 " move %0, $1 \n" 1888 " ehb \n" 1889 " .set pop \n" 1890 : "=r" (res)); 1891 1892 instruction_hazard(); 1893 #endif 1894 1895 __asm__ __volatile__( 1896 ".set noreorder\n\t" 1897 "tlbr\n\t" 1898 ".set reorder"); 1899 1900 #if MIPS34K_MISSED_ITLB_WAR 1901 if ((res & _ULCAST_(1))) 1902 __asm__ __volatile__( 1903 " .set push \n" 1904 " .set noreorder \n" 1905 " .set noat \n" 1906 " .set mips32r2 \n" 1907 " .word 0x41600021 # evpe \n" 1908 " ehb \n" 1909 " .set pop \n"); 1910 #endif 1911 } 1912 1913 static inline void tlb_write_indexed(void) 1914 { 1915 __asm__ __volatile__( 1916 ".set noreorder\n\t" 1917 "tlbwi\n\t" 1918 ".set reorder"); 1919 } 1920 1921 static inline void tlb_write_random(void) 1922 { 1923 __asm__ __volatile__( 1924 ".set noreorder\n\t" 1925 "tlbwr\n\t" 1926 ".set reorder"); 1927 } 1928 1929 /* 1930 * Manipulate bits in a c0 register. 1931 */ 1932 #define __BUILD_SET_C0(name) \ 1933 static inline unsigned int \ 1934 set_c0_##name(unsigned int set) \ 1935 { \ 1936 unsigned int res, new; \ 1937 \ 1938 res = read_c0_##name(); \ 1939 new = res | set; \ 1940 write_c0_##name(new); \ 1941 \ 1942 return res; \ 1943 } \ 1944 \ 1945 static inline unsigned int \ 1946 clear_c0_##name(unsigned int clear) \ 1947 { \ 1948 unsigned int res, new; \ 1949 \ 1950 res = read_c0_##name(); \ 1951 new = res & ~clear; \ 1952 write_c0_##name(new); \ 1953 \ 1954 return res; \ 1955 } \ 1956 \ 1957 static inline unsigned int \ 1958 change_c0_##name(unsigned int change, unsigned int val) \ 1959 { \ 1960 unsigned int res, new; \ 1961 \ 1962 res = read_c0_##name(); \ 1963 new = res & ~change; \ 1964 new |= (val & change); \ 1965 write_c0_##name(new); \ 1966 \ 1967 return res; \ 1968 } 1969 1970 __BUILD_SET_C0(status) 1971 __BUILD_SET_C0(cause) 1972 __BUILD_SET_C0(config) 1973 __BUILD_SET_C0(config5) 1974 __BUILD_SET_C0(intcontrol) 1975 __BUILD_SET_C0(intctl) 1976 __BUILD_SET_C0(srsmap) 1977 __BUILD_SET_C0(pagegrain) 1978 __BUILD_SET_C0(brcm_config_0) 1979 __BUILD_SET_C0(brcm_bus_pll) 1980 __BUILD_SET_C0(brcm_reset) 1981 __BUILD_SET_C0(brcm_cmt_intr) 1982 __BUILD_SET_C0(brcm_cmt_ctrl) 1983 __BUILD_SET_C0(brcm_config) 1984 __BUILD_SET_C0(brcm_mode) 1985 1986 /* 1987 * Return low 10 bits of ebase. 1988 * Note that under KVM (MIPSVZ) this returns vcpu id. 1989 */ 1990 static inline unsigned int get_ebase_cpunum(void) 1991 { 1992 return read_c0_ebase() & 0x3ff; 1993 } 1994 1995 #endif /* !__ASSEMBLY__ */ 1996 1997 #endif /* _ASM_MIPSREGS_H */ 1998