1 /* 2 * Copyright (C) 1994, 1995 Waldorf GmbH 3 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 4 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 5 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 6 * Author: Maciej W. Rozycki <macro@mips.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 #ifndef _ASM_IO_H 11 #define _ASM_IO_H 12 13 #include <linux/compiler.h> 14 #include <linux/types.h> 15 16 #include <asm/addrspace.h> 17 #include <asm/byteorder.h> 18 #include <asm/cpu-features.h> 19 #include <asm/pgtable-bits.h> 20 #include <asm/processor.h> 21 #include <asm/string.h> 22 23 #include <ioremap.h> 24 #include <mangle-port.h> 25 #include <spaces.h> 26 27 /* 28 * Slowdown I/O port space accesses for antique hardware. 29 */ 30 #undef CONF_SLOWDOWN_IO 31 32 /* 33 * Raw operations are never swapped in software. OTOH values that raw 34 * operations are working on may or may not have been swapped by the bus 35 * hardware. An example use would be for flash memory that's used for 36 * execute in place. 37 */ 38 # define __raw_ioswabb(a, x) (x) 39 # define __raw_ioswabw(a, x) (x) 40 # define __raw_ioswabl(a, x) (x) 41 # define __raw_ioswabq(a, x) (x) 42 # define ____raw_ioswabq(a, x) (x) 43 44 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 45 46 #define IO_SPACE_LIMIT 0xffff 47 48 /* 49 * On MIPS I/O ports are memory mapped, so we access them using normal 50 * load/store instructions. mips_io_port_base is the virtual address to 51 * which all ports are being mapped. For sake of efficiency some code 52 * assumes that this is an address that can be loaded with a single lui 53 * instruction, so the lower 16 bits must be zero. Should be true on 54 * on any sane architecture; generic code does not use this assumption. 55 */ 56 extern const unsigned long mips_io_port_base; 57 58 /* 59 * Gcc will generate code to load the value of mips_io_port_base after each 60 * function call which may be fairly wasteful in some cases. So we don't 61 * play quite by the book. We tell gcc mips_io_port_base is a long variable 62 * which solves the code generation issue. Now we need to violate the 63 * aliasing rules a little to make initialization possible and finally we 64 * will need the barrier() to fight side effects of the aliasing chat. 65 * This trickery will eventually collapse under gcc's optimizer. Oh well. 66 */ 67 static inline void set_io_port_base(unsigned long base) 68 { 69 * (unsigned long *) &mips_io_port_base = base; 70 barrier(); 71 } 72 73 /* 74 * Thanks to James van Artsdalen for a better timing-fix than 75 * the two short jumps: using outb's to a nonexistent port seems 76 * to guarantee better timings even on fast machines. 77 * 78 * On the other hand, I'd like to be sure of a non-existent port: 79 * I feel a bit unsafe about using 0x80 (should be safe, though) 80 * 81 * Linus 82 * 83 */ 84 85 #define __SLOW_DOWN_IO \ 86 __asm__ __volatile__( \ 87 "sb\t$0,0x80(%0)" \ 88 : : "r" (mips_io_port_base)); 89 90 #ifdef CONF_SLOWDOWN_IO 91 #ifdef REALLY_SLOW_IO 92 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } 93 #else 94 #define SLOW_DOWN_IO __SLOW_DOWN_IO 95 #endif 96 #else 97 #define SLOW_DOWN_IO 98 #endif 99 100 /* 101 * virt_to_phys - map virtual addresses to physical 102 * @address: address to remap 103 * 104 * The returned physical address is the physical (CPU) mapping for 105 * the memory address given. It is only valid to use this function on 106 * addresses directly mapped or allocated via kmalloc. 107 * 108 * This function does not give bus mappings for DMA transfers. In 109 * almost all conceivable cases a device driver should not be using 110 * this function 111 */ 112 static inline unsigned long virt_to_phys(volatile const void *address) 113 { 114 unsigned long addr = (unsigned long)address; 115 116 /* this corresponds to kernel implementation of __pa() */ 117 #ifdef CONFIG_64BIT 118 if (addr < CKSEG0) 119 return XPHYSADDR(addr); 120 121 return CPHYSADDR(addr); 122 #else 123 return addr - PAGE_OFFSET + PHYS_OFFSET; 124 #endif 125 } 126 127 /* 128 * phys_to_virt - map physical address to virtual 129 * @address: address to remap 130 * 131 * The returned virtual address is a current CPU mapping for 132 * the memory address given. It is only valid to use this function on 133 * addresses that have a kernel mapping 134 * 135 * This function does not handle bus mappings for DMA transfers. In 136 * almost all conceivable cases a device driver should not be using 137 * this function 138 */ 139 static inline void *phys_to_virt(unsigned long address) 140 { 141 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 142 } 143 144 /* 145 * ISA I/O bus memory addresses are 1:1 with the physical address. 146 */ 147 static inline unsigned long isa_virt_to_bus(volatile void *address) 148 { 149 return (unsigned long)address - PAGE_OFFSET; 150 } 151 152 static inline void *isa_bus_to_virt(unsigned long address) 153 { 154 return (void *)(address + PAGE_OFFSET); 155 } 156 157 #define isa_page_to_bus page_to_phys 158 159 /* 160 * However PCI ones are not necessarily 1:1 and therefore these interfaces 161 * are forbidden in portable PCI drivers. 162 * 163 * Allow them for x86 for legacy drivers, though. 164 */ 165 #define virt_to_bus virt_to_phys 166 #define bus_to_virt phys_to_virt 167 168 static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size, 169 unsigned long flags) 170 { 171 void __iomem *addr; 172 phys_addr_t phys_addr; 173 174 addr = plat_ioremap(offset, size, flags); 175 if (addr) 176 return addr; 177 178 phys_addr = fixup_bigphys_addr(offset, size); 179 return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); 180 } 181 182 /* 183 * ioremap - map bus memory into CPU space 184 * @offset: bus address of the memory 185 * @size: size of the resource to map 186 * 187 * ioremap performs a platform specific sequence of operations to 188 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 189 * writew/writel functions and the other mmio helpers. The returned 190 * address is not guaranteed to be usable directly as a virtual 191 * address. 192 */ 193 #define ioremap(offset, size) \ 194 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 195 196 /* 197 * ioremap_nocache - map bus memory into CPU space 198 * @offset: bus address of the memory 199 * @size: size of the resource to map 200 * 201 * ioremap_nocache performs a platform specific sequence of operations to 202 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 203 * writew/writel functions and the other mmio helpers. The returned 204 * address is not guaranteed to be usable directly as a virtual 205 * address. 206 * 207 * This version of ioremap ensures that the memory is marked uncachable 208 * on the CPU as well as honouring existing caching rules from things like 209 * the PCI bus. Note that there are other caches and buffers on many 210 * busses. In particular driver authors should read up on PCI writes 211 * 212 * It's useful if some control registers are in such an area and 213 * write combining or read caching is not desirable: 214 */ 215 #define ioremap_nocache(offset, size) \ 216 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 217 #define ioremap_uc ioremap_nocache 218 219 /* 220 * ioremap_cachable - map bus memory into CPU space 221 * @offset: bus address of the memory 222 * @size: size of the resource to map 223 * 224 * ioremap_nocache performs a platform specific sequence of operations to 225 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 226 * writew/writel functions and the other mmio helpers. The returned 227 * address is not guaranteed to be usable directly as a virtual 228 * address. 229 * 230 * This version of ioremap ensures that the memory is marked cachable by 231 * the CPU. Also enables full write-combining. Useful for some 232 * memory-like regions on I/O busses. 233 */ 234 #define ioremap_cachable(offset, size) \ 235 __ioremap_mode((offset), (size), _page_cachable_default) 236 237 /* 238 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow 239 * requests a cachable mapping, ioremap_uncached_accelerated requests a 240 * mapping using the uncached accelerated mode which isn't supported on 241 * all processors. 242 */ 243 #define ioremap_cacheable_cow(offset, size) \ 244 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) 245 #define ioremap_uncached_accelerated(offset, size) \ 246 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) 247 248 static inline void iounmap(const volatile void __iomem *addr) 249 { 250 plat_iounmap(addr); 251 } 252 253 #ifdef CONFIG_CPU_CAVIUM_OCTEON 254 #define war_octeon_io_reorder_wmb() wmb() 255 #else 256 #define war_octeon_io_reorder_wmb() do { } while (0) 257 #endif 258 259 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 260 \ 261 static inline void pfx##write##bwlq(type val, \ 262 volatile void __iomem *mem) \ 263 { \ 264 volatile type *__mem; \ 265 type __val; \ 266 \ 267 war_octeon_io_reorder_wmb(); \ 268 \ 269 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 270 \ 271 __val = pfx##ioswab##bwlq(__mem, val); \ 272 \ 273 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 274 *__mem = __val; \ 275 else if (cpu_has_64bits) { \ 276 type __tmp; \ 277 \ 278 __asm__ __volatile__( \ 279 ".set arch=r4000" "\t\t# __writeq""\n\t" \ 280 "dsll32 %L0, %L0, 0" "\n\t" \ 281 "dsrl32 %L0, %L0, 0" "\n\t" \ 282 "dsll32 %M0, %M0, 0" "\n\t" \ 283 "or %L0, %L0, %M0" "\n\t" \ 284 "sd %L0, %2" "\n\t" \ 285 ".set mips0" "\n" \ 286 : "=r" (__tmp) \ 287 : "0" (__val), "m" (*__mem)); \ 288 } else \ 289 BUG(); \ 290 } \ 291 \ 292 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 293 { \ 294 volatile type *__mem; \ 295 type __val; \ 296 \ 297 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 298 \ 299 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 300 __val = *__mem; \ 301 else if (cpu_has_64bits) { \ 302 __asm__ __volatile__( \ 303 ".set arch=r4000" "\t\t# __readq" "\n\t" \ 304 "ld %L0, %1" "\n\t" \ 305 "dsra32 %M0, %L0, 0" "\n\t" \ 306 "sll %L0, %L0, 0" "\n\t" \ 307 ".set mips0" "\n" \ 308 : "=r" (__val) \ 309 : "m" (*__mem)); \ 310 } else { \ 311 __val = 0; \ 312 BUG(); \ 313 } \ 314 \ 315 return pfx##ioswab##bwlq(__mem, __val); \ 316 } 317 318 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 319 \ 320 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 321 { \ 322 volatile type *__addr; \ 323 type __val; \ 324 \ 325 war_octeon_io_reorder_wmb(); \ 326 \ 327 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 328 \ 329 __val = pfx##ioswab##bwlq(__addr, val); \ 330 \ 331 /* Really, we want this to be atomic */ \ 332 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 333 \ 334 *__addr = __val; \ 335 slow; \ 336 } \ 337 \ 338 static inline type pfx##in##bwlq##p(unsigned long port) \ 339 { \ 340 volatile type *__addr; \ 341 type __val; \ 342 \ 343 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 344 \ 345 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 346 \ 347 __val = *__addr; \ 348 slow; \ 349 \ 350 return pfx##ioswab##bwlq(__addr, __val); \ 351 } 352 353 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \ 354 \ 355 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) 356 357 #define BUILDIO_MEM(bwlq, type) \ 358 \ 359 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ 360 __BUILD_MEMORY_PFX(, bwlq, type) \ 361 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \ 362 363 BUILDIO_MEM(b, u8) 364 BUILDIO_MEM(w, u16) 365 BUILDIO_MEM(l, u32) 366 BUILDIO_MEM(q, u64) 367 368 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 369 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 370 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 371 372 #define BUILDIO_IOPORT(bwlq, type) \ 373 __BUILD_IOPORT_PFX(, bwlq, type) \ 374 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 375 376 BUILDIO_IOPORT(b, u8) 377 BUILDIO_IOPORT(w, u16) 378 BUILDIO_IOPORT(l, u32) 379 #ifdef CONFIG_64BIT 380 BUILDIO_IOPORT(q, u64) 381 #endif 382 383 #define __BUILDIO(bwlq, type) \ 384 \ 385 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) 386 387 __BUILDIO(q, u64) 388 389 #define readb_relaxed readb 390 #define readw_relaxed readw 391 #define readl_relaxed readl 392 #define readq_relaxed readq 393 394 #define writeb_relaxed writeb 395 #define writew_relaxed writew 396 #define writel_relaxed writel 397 #define writeq_relaxed writeq 398 399 #define readb_be(addr) \ 400 __raw_readb((__force unsigned *)(addr)) 401 #define readw_be(addr) \ 402 be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 403 #define readl_be(addr) \ 404 be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 405 #define readq_be(addr) \ 406 be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 407 408 #define writeb_be(val, addr) \ 409 __raw_writeb((val), (__force unsigned *)(addr)) 410 #define writew_be(val, addr) \ 411 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 412 #define writel_be(val, addr) \ 413 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 414 #define writeq_be(val, addr) \ 415 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 416 417 /* 418 * Some code tests for these symbols 419 */ 420 #define readq readq 421 #define writeq writeq 422 423 #define __BUILD_MEMORY_STRING(bwlq, type) \ 424 \ 425 static inline void writes##bwlq(volatile void __iomem *mem, \ 426 const void *addr, unsigned int count) \ 427 { \ 428 const volatile type *__addr = addr; \ 429 \ 430 while (count--) { \ 431 __mem_write##bwlq(*__addr, mem); \ 432 __addr++; \ 433 } \ 434 } \ 435 \ 436 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 437 unsigned int count) \ 438 { \ 439 volatile type *__addr = addr; \ 440 \ 441 while (count--) { \ 442 *__addr = __mem_read##bwlq(mem); \ 443 __addr++; \ 444 } \ 445 } 446 447 #define __BUILD_IOPORT_STRING(bwlq, type) \ 448 \ 449 static inline void outs##bwlq(unsigned long port, const void *addr, \ 450 unsigned int count) \ 451 { \ 452 const volatile type *__addr = addr; \ 453 \ 454 while (count--) { \ 455 __mem_out##bwlq(*__addr, port); \ 456 __addr++; \ 457 } \ 458 } \ 459 \ 460 static inline void ins##bwlq(unsigned long port, void *addr, \ 461 unsigned int count) \ 462 { \ 463 volatile type *__addr = addr; \ 464 \ 465 while (count--) { \ 466 *__addr = __mem_in##bwlq(port); \ 467 __addr++; \ 468 } \ 469 } 470 471 #define BUILDSTRING(bwlq, type) \ 472 \ 473 __BUILD_MEMORY_STRING(bwlq, type) \ 474 __BUILD_IOPORT_STRING(bwlq, type) 475 476 BUILDSTRING(b, u8) 477 BUILDSTRING(w, u16) 478 BUILDSTRING(l, u32) 479 #ifdef CONFIG_64BIT 480 BUILDSTRING(q, u64) 481 #endif 482 483 484 #ifdef CONFIG_CPU_CAVIUM_OCTEON 485 #define mmiowb() wmb() 486 #else 487 /* Depends on MIPS II instruction set */ 488 #define mmiowb() asm volatile ("sync" ::: "memory") 489 #endif 490 491 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 492 { 493 memset((void __force *)addr, val, count); 494 } 495 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 496 { 497 memcpy(dst, (void __force *)src, count); 498 } 499 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 500 { 501 memcpy((void __force *)dst, src, count); 502 } 503 504 /* 505 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 506 * Avoid interrupt mucking, just adjust the address for 4-byte access. 507 * Assume the addresses are 8-byte aligned. 508 */ 509 #ifdef __MIPSEB__ 510 #define __CSR_32_ADJUST 4 511 #else 512 #define __CSR_32_ADJUST 0 513 #endif 514 515 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 516 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 517 518 /* 519 * U-Boot specific 520 */ 521 #define sync() mmiowb() 522 523 #define MAP_NOCACHE (1) 524 #define MAP_WRCOMBINE (0) 525 #define MAP_WRBACK (0) 526 #define MAP_WRTHROUGH (0) 527 528 static inline void * 529 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) 530 { 531 if (flags == MAP_NOCACHE) 532 return ioremap(paddr, len); 533 534 return (void *)paddr; 535 } 536 537 /* 538 * Take down a mapping set up by map_physmem(). 539 */ 540 static inline void unmap_physmem(void *vaddr, unsigned long flags) 541 { 542 } 543 544 #define __BUILD_CLRBITS(bwlq, sfx, end, type) \ 545 \ 546 static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \ 547 { \ 548 type __val = __raw_read##bwlq(mem); \ 549 __val = end##_to_cpu(__val); \ 550 __val &= ~clr; \ 551 __val = cpu_to_##end(__val); \ 552 __raw_write##bwlq(__val, mem); \ 553 } 554 555 #define __BUILD_SETBITS(bwlq, sfx, end, type) \ 556 \ 557 static inline void setbits_##sfx(volatile void __iomem *mem, type set) \ 558 { \ 559 type __val = __raw_read##bwlq(mem); \ 560 __val = end##_to_cpu(__val); \ 561 __val |= set; \ 562 __val = cpu_to_##end(__val); \ 563 __raw_write##bwlq(__val, mem); \ 564 } 565 566 #define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \ 567 \ 568 static inline void clrsetbits_##sfx(volatile void __iomem *mem, \ 569 type clr, type set) \ 570 { \ 571 type __val = __raw_read##bwlq(mem); \ 572 __val = end##_to_cpu(__val); \ 573 __val &= ~clr; \ 574 __val |= set; \ 575 __val = cpu_to_##end(__val); \ 576 __raw_write##bwlq(__val, mem); \ 577 } 578 579 #define BUILD_CLRSETBITS(bwlq, sfx, end, type) \ 580 \ 581 __BUILD_CLRBITS(bwlq, sfx, end, type) \ 582 __BUILD_SETBITS(bwlq, sfx, end, type) \ 583 __BUILD_CLRSETBITS(bwlq, sfx, end, type) 584 585 #define __to_cpu(v) (v) 586 #define cpu_to__(v) (v) 587 588 BUILD_CLRSETBITS(b, 8, _, u8) 589 BUILD_CLRSETBITS(w, le16, le16, u16) 590 BUILD_CLRSETBITS(w, be16, be16, u16) 591 BUILD_CLRSETBITS(w, 16, _, u16) 592 BUILD_CLRSETBITS(l, le32, le32, u32) 593 BUILD_CLRSETBITS(l, be32, be32, u32) 594 BUILD_CLRSETBITS(l, 32, _, u32) 595 BUILD_CLRSETBITS(q, le64, le64, u64) 596 BUILD_CLRSETBITS(q, be64, be64, u64) 597 BUILD_CLRSETBITS(q, 64, _, u64) 598 599 #endif /* _ASM_IO_H */ 600