1819833afSPeter Tyser /* 2819833afSPeter Tyser * Copyright (C) 1994, 1995 Waldorf GmbH 323ff8633SDaniel Schwierzeck * Copyright (C) 1994 - 2000, 06 Ralf Baechle 4819833afSPeter Tyser * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 523ff8633SDaniel Schwierzeck * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 623ff8633SDaniel Schwierzeck * Author: Maciej W. Rozycki <macro@mips.com> 723ff8633SDaniel Schwierzeck * 823ff8633SDaniel Schwierzeck * SPDX-License-Identifier: GPL-2.0 9819833afSPeter Tyser */ 10819833afSPeter Tyser #ifndef _ASM_IO_H 11819833afSPeter Tyser #define _ASM_IO_H 12819833afSPeter Tyser 1323ff8633SDaniel Schwierzeck #include <linux/compiler.h> 1423ff8633SDaniel Schwierzeck #include <linux/types.h> 1523ff8633SDaniel Schwierzeck 16819833afSPeter Tyser #include <asm/addrspace.h> 17819833afSPeter Tyser #include <asm/byteorder.h> 1823ff8633SDaniel Schwierzeck #include <asm/cpu-features.h> 1923ff8633SDaniel Schwierzeck #include <asm/pgtable-bits.h> 2023ff8633SDaniel Schwierzeck #include <asm/processor.h> 2123ff8633SDaniel Schwierzeck #include <asm/string.h> 2223ff8633SDaniel Schwierzeck 2323ff8633SDaniel Schwierzeck #include <ioremap.h> 2423ff8633SDaniel Schwierzeck #include <mangle-port.h> 2523ff8633SDaniel Schwierzeck #include <spaces.h> 26819833afSPeter Tyser 27819833afSPeter Tyser /* 28819833afSPeter Tyser * Slowdown I/O port space accesses for antique hardware. 29819833afSPeter Tyser */ 30819833afSPeter Tyser #undef CONF_SLOWDOWN_IO 31819833afSPeter Tyser 32819833afSPeter Tyser /* 3323ff8633SDaniel Schwierzeck * Raw operations are never swapped in software. OTOH values that raw 3423ff8633SDaniel Schwierzeck * operations are working on may or may not have been swapped by the bus 3523ff8633SDaniel Schwierzeck * hardware. An example use would be for flash memory that's used for 3623ff8633SDaniel Schwierzeck * execute in place. 37819833afSPeter Tyser */ 3823ff8633SDaniel Schwierzeck # define __raw_ioswabb(a, x) (x) 3923ff8633SDaniel Schwierzeck # define __raw_ioswabw(a, x) (x) 4023ff8633SDaniel Schwierzeck # define __raw_ioswabl(a, x) (x) 4123ff8633SDaniel Schwierzeck # define __raw_ioswabq(a, x) (x) 4223ff8633SDaniel Schwierzeck # define ____raw_ioswabq(a, x) (x) 43819833afSPeter Tyser 4423ff8633SDaniel Schwierzeck /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 45819833afSPeter Tyser 4623ff8633SDaniel Schwierzeck #define IO_SPACE_LIMIT 0xffff 47819833afSPeter Tyser 48819833afSPeter Tyser /* 49819833afSPeter Tyser * On MIPS I/O ports are memory mapped, so we access them using normal 50819833afSPeter Tyser * load/store instructions. mips_io_port_base is the virtual address to 51819833afSPeter Tyser * which all ports are being mapped. For sake of efficiency some code 52819833afSPeter Tyser * assumes that this is an address that can be loaded with a single lui 53819833afSPeter Tyser * instruction, so the lower 16 bits must be zero. Should be true on 54819833afSPeter Tyser * on any sane architecture; generic code does not use this assumption. 55819833afSPeter Tyser */ 56819833afSPeter Tyser extern const unsigned long mips_io_port_base; 57819833afSPeter Tyser 58819833afSPeter Tyser /* 59819833afSPeter Tyser * Gcc will generate code to load the value of mips_io_port_base after each 60819833afSPeter Tyser * function call which may be fairly wasteful in some cases. So we don't 61819833afSPeter Tyser * play quite by the book. We tell gcc mips_io_port_base is a long variable 62819833afSPeter Tyser * which solves the code generation issue. Now we need to violate the 63819833afSPeter Tyser * aliasing rules a little to make initialization possible and finally we 64819833afSPeter Tyser * will need the barrier() to fight side effects of the aliasing chat. 65819833afSPeter Tyser * This trickery will eventually collapse under gcc's optimizer. Oh well. 66819833afSPeter Tyser */ 67819833afSPeter Tyser static inline void set_io_port_base(unsigned long base) 68819833afSPeter Tyser { 69819833afSPeter Tyser * (unsigned long *) &mips_io_port_base = base; 7023ff8633SDaniel Schwierzeck barrier(); 71819833afSPeter Tyser } 72819833afSPeter Tyser 73819833afSPeter Tyser /* 74819833afSPeter Tyser * Thanks to James van Artsdalen for a better timing-fix than 75819833afSPeter Tyser * the two short jumps: using outb's to a nonexistent port seems 76819833afSPeter Tyser * to guarantee better timings even on fast machines. 77819833afSPeter Tyser * 78819833afSPeter Tyser * On the other hand, I'd like to be sure of a non-existent port: 79819833afSPeter Tyser * I feel a bit unsafe about using 0x80 (should be safe, though) 80819833afSPeter Tyser * 81819833afSPeter Tyser * Linus 82819833afSPeter Tyser * 83819833afSPeter Tyser */ 84819833afSPeter Tyser 85819833afSPeter Tyser #define __SLOW_DOWN_IO \ 86819833afSPeter Tyser __asm__ __volatile__( \ 87819833afSPeter Tyser "sb\t$0,0x80(%0)" \ 88819833afSPeter Tyser : : "r" (mips_io_port_base)); 89819833afSPeter Tyser 90819833afSPeter Tyser #ifdef CONF_SLOWDOWN_IO 91819833afSPeter Tyser #ifdef REALLY_SLOW_IO 92819833afSPeter Tyser #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } 93819833afSPeter Tyser #else 94819833afSPeter Tyser #define SLOW_DOWN_IO __SLOW_DOWN_IO 95819833afSPeter Tyser #endif 96819833afSPeter Tyser #else 97819833afSPeter Tyser #define SLOW_DOWN_IO 98819833afSPeter Tyser #endif 99819833afSPeter Tyser 100819833afSPeter Tyser /* 10123ff8633SDaniel Schwierzeck * virt_to_phys - map virtual addresses to physical 10223ff8633SDaniel Schwierzeck * @address: address to remap 10323ff8633SDaniel Schwierzeck * 10423ff8633SDaniel Schwierzeck * The returned physical address is the physical (CPU) mapping for 10523ff8633SDaniel Schwierzeck * the memory address given. It is only valid to use this function on 10623ff8633SDaniel Schwierzeck * addresses directly mapped or allocated via kmalloc. 10723ff8633SDaniel Schwierzeck * 10823ff8633SDaniel Schwierzeck * This function does not give bus mappings for DMA transfers. In 10923ff8633SDaniel Schwierzeck * almost all conceivable cases a device driver should not be using 11023ff8633SDaniel Schwierzeck * this function 111819833afSPeter Tyser */ 11223ff8633SDaniel Schwierzeck static inline unsigned long virt_to_phys(volatile const void *address) 113819833afSPeter Tyser { 11423ff8633SDaniel Schwierzeck unsigned long addr = (unsigned long)address; 11523ff8633SDaniel Schwierzeck 11623ff8633SDaniel Schwierzeck /* this corresponds to kernel implementation of __pa() */ 11723ff8633SDaniel Schwierzeck #ifdef CONFIG_64BIT 11823ff8633SDaniel Schwierzeck if (addr < CKSEG0) 11923ff8633SDaniel Schwierzeck return XPHYSADDR(addr); 12023ff8633SDaniel Schwierzeck 12123ff8633SDaniel Schwierzeck return CPHYSADDR(addr); 122090854c8SZhi-zhou Zhang #else 12323ff8633SDaniel Schwierzeck return addr - PAGE_OFFSET + PHYS_OFFSET; 124090854c8SZhi-zhou Zhang #endif 125819833afSPeter Tyser } 126819833afSPeter Tyser 12723ff8633SDaniel Schwierzeck /* 12823ff8633SDaniel Schwierzeck * phys_to_virt - map physical address to virtual 12923ff8633SDaniel Schwierzeck * @address: address to remap 13023ff8633SDaniel Schwierzeck * 13123ff8633SDaniel Schwierzeck * The returned virtual address is a current CPU mapping for 13223ff8633SDaniel Schwierzeck * the memory address given. It is only valid to use this function on 13323ff8633SDaniel Schwierzeck * addresses that have a kernel mapping 13423ff8633SDaniel Schwierzeck * 13523ff8633SDaniel Schwierzeck * This function does not handle bus mappings for DMA transfers. In 13623ff8633SDaniel Schwierzeck * almost all conceivable cases a device driver should not be using 13723ff8633SDaniel Schwierzeck * this function 13823ff8633SDaniel Schwierzeck */ 139b11c5d1dSDaniel Schwierzeck static inline void *phys_to_virt(unsigned long address) 140819833afSPeter Tyser { 14123ff8633SDaniel Schwierzeck return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 142819833afSPeter Tyser } 143819833afSPeter Tyser 144819833afSPeter Tyser /* 14523ff8633SDaniel Schwierzeck * ISA I/O bus memory addresses are 1:1 with the physical address. 146819833afSPeter Tyser */ 14723ff8633SDaniel Schwierzeck static inline unsigned long isa_virt_to_bus(volatile void *address) 148819833afSPeter Tyser { 14923ff8633SDaniel Schwierzeck return (unsigned long)address - PAGE_OFFSET; 150819833afSPeter Tyser } 151819833afSPeter Tyser 15223ff8633SDaniel Schwierzeck static inline void *isa_bus_to_virt(unsigned long address) 153819833afSPeter Tyser { 15423ff8633SDaniel Schwierzeck return (void *)(address + PAGE_OFFSET); 155819833afSPeter Tyser } 156819833afSPeter Tyser 15723ff8633SDaniel Schwierzeck #define isa_page_to_bus page_to_phys 158819833afSPeter Tyser 159819833afSPeter Tyser /* 16023ff8633SDaniel Schwierzeck * However PCI ones are not necessarily 1:1 and therefore these interfaces 16123ff8633SDaniel Schwierzeck * are forbidden in portable PCI drivers. 162819833afSPeter Tyser * 16323ff8633SDaniel Schwierzeck * Allow them for x86 for legacy drivers, though. 164819833afSPeter Tyser */ 16523ff8633SDaniel Schwierzeck #define virt_to_bus virt_to_phys 16623ff8633SDaniel Schwierzeck #define bus_to_virt phys_to_virt 167819833afSPeter Tyser 16823ff8633SDaniel Schwierzeck static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size, 16923ff8633SDaniel Schwierzeck unsigned long flags) 170819833afSPeter Tyser { 17123ff8633SDaniel Schwierzeck void __iomem *addr; 17223ff8633SDaniel Schwierzeck phys_addr_t phys_addr; 17323ff8633SDaniel Schwierzeck 17423ff8633SDaniel Schwierzeck addr = plat_ioremap(offset, size, flags); 17523ff8633SDaniel Schwierzeck if (addr) 17623ff8633SDaniel Schwierzeck return addr; 17723ff8633SDaniel Schwierzeck 17823ff8633SDaniel Schwierzeck phys_addr = fixup_bigphys_addr(offset, size); 17923ff8633SDaniel Schwierzeck return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); 180819833afSPeter Tyser } 181819833afSPeter Tyser 182819833afSPeter Tyser /* 18323ff8633SDaniel Schwierzeck * ioremap - map bus memory into CPU space 18423ff8633SDaniel Schwierzeck * @offset: bus address of the memory 18523ff8633SDaniel Schwierzeck * @size: size of the resource to map 18623ff8633SDaniel Schwierzeck * 18723ff8633SDaniel Schwierzeck * ioremap performs a platform specific sequence of operations to 18823ff8633SDaniel Schwierzeck * make bus memory CPU accessible via the readb/readw/readl/writeb/ 18923ff8633SDaniel Schwierzeck * writew/writel functions and the other mmio helpers. The returned 19023ff8633SDaniel Schwierzeck * address is not guaranteed to be usable directly as a virtual 19123ff8633SDaniel Schwierzeck * address. 192819833afSPeter Tyser */ 19323ff8633SDaniel Schwierzeck #define ioremap(offset, size) \ 19423ff8633SDaniel Schwierzeck __ioremap_mode((offset), (size), _CACHE_UNCACHED) 19523ff8633SDaniel Schwierzeck 19623ff8633SDaniel Schwierzeck /* 19723ff8633SDaniel Schwierzeck * ioremap_nocache - map bus memory into CPU space 19823ff8633SDaniel Schwierzeck * @offset: bus address of the memory 19923ff8633SDaniel Schwierzeck * @size: size of the resource to map 20023ff8633SDaniel Schwierzeck * 20123ff8633SDaniel Schwierzeck * ioremap_nocache performs a platform specific sequence of operations to 20223ff8633SDaniel Schwierzeck * make bus memory CPU accessible via the readb/readw/readl/writeb/ 20323ff8633SDaniel Schwierzeck * writew/writel functions and the other mmio helpers. The returned 20423ff8633SDaniel Schwierzeck * address is not guaranteed to be usable directly as a virtual 20523ff8633SDaniel Schwierzeck * address. 20623ff8633SDaniel Schwierzeck * 20723ff8633SDaniel Schwierzeck * This version of ioremap ensures that the memory is marked uncachable 20823ff8633SDaniel Schwierzeck * on the CPU as well as honouring existing caching rules from things like 20923ff8633SDaniel Schwierzeck * the PCI bus. Note that there are other caches and buffers on many 21023ff8633SDaniel Schwierzeck * busses. In particular driver authors should read up on PCI writes 21123ff8633SDaniel Schwierzeck * 21223ff8633SDaniel Schwierzeck * It's useful if some control registers are in such an area and 21323ff8633SDaniel Schwierzeck * write combining or read caching is not desirable: 21423ff8633SDaniel Schwierzeck */ 21523ff8633SDaniel Schwierzeck #define ioremap_nocache(offset, size) \ 21623ff8633SDaniel Schwierzeck __ioremap_mode((offset), (size), _CACHE_UNCACHED) 21723ff8633SDaniel Schwierzeck #define ioremap_uc ioremap_nocache 21823ff8633SDaniel Schwierzeck 21923ff8633SDaniel Schwierzeck /* 22023ff8633SDaniel Schwierzeck * ioremap_cachable - map bus memory into CPU space 22123ff8633SDaniel Schwierzeck * @offset: bus address of the memory 22223ff8633SDaniel Schwierzeck * @size: size of the resource to map 22323ff8633SDaniel Schwierzeck * 22423ff8633SDaniel Schwierzeck * ioremap_nocache performs a platform specific sequence of operations to 22523ff8633SDaniel Schwierzeck * make bus memory CPU accessible via the readb/readw/readl/writeb/ 22623ff8633SDaniel Schwierzeck * writew/writel functions and the other mmio helpers. The returned 22723ff8633SDaniel Schwierzeck * address is not guaranteed to be usable directly as a virtual 22823ff8633SDaniel Schwierzeck * address. 22923ff8633SDaniel Schwierzeck * 23023ff8633SDaniel Schwierzeck * This version of ioremap ensures that the memory is marked cachable by 23123ff8633SDaniel Schwierzeck * the CPU. Also enables full write-combining. Useful for some 23223ff8633SDaniel Schwierzeck * memory-like regions on I/O busses. 23323ff8633SDaniel Schwierzeck */ 23423ff8633SDaniel Schwierzeck #define ioremap_cachable(offset, size) \ 23523ff8633SDaniel Schwierzeck __ioremap_mode((offset), (size), _page_cachable_default) 23623ff8633SDaniel Schwierzeck 23723ff8633SDaniel Schwierzeck /* 23823ff8633SDaniel Schwierzeck * These two are MIPS specific ioremap variant. ioremap_cacheable_cow 23923ff8633SDaniel Schwierzeck * requests a cachable mapping, ioremap_uncached_accelerated requests a 24023ff8633SDaniel Schwierzeck * mapping using the uncached accelerated mode which isn't supported on 24123ff8633SDaniel Schwierzeck * all processors. 24223ff8633SDaniel Schwierzeck */ 24323ff8633SDaniel Schwierzeck #define ioremap_cacheable_cow(offset, size) \ 24423ff8633SDaniel Schwierzeck __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) 24523ff8633SDaniel Schwierzeck #define ioremap_uncached_accelerated(offset, size) \ 24623ff8633SDaniel Schwierzeck __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) 24723ff8633SDaniel Schwierzeck 24823ff8633SDaniel Schwierzeck static inline void iounmap(const volatile void __iomem *addr) 24923ff8633SDaniel Schwierzeck { 25023ff8633SDaniel Schwierzeck plat_iounmap(addr); 25123ff8633SDaniel Schwierzeck } 25223ff8633SDaniel Schwierzeck 25323ff8633SDaniel Schwierzeck #ifdef CONFIG_CPU_CAVIUM_OCTEON 25423ff8633SDaniel Schwierzeck #define war_octeon_io_reorder_wmb() wmb() 25523ff8633SDaniel Schwierzeck #else 25623ff8633SDaniel Schwierzeck #define war_octeon_io_reorder_wmb() do { } while (0) 25723ff8633SDaniel Schwierzeck #endif 25823ff8633SDaniel Schwierzeck 25923ff8633SDaniel Schwierzeck #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 26023ff8633SDaniel Schwierzeck \ 26123ff8633SDaniel Schwierzeck static inline void pfx##write##bwlq(type val, \ 26223ff8633SDaniel Schwierzeck volatile void __iomem *mem) \ 26323ff8633SDaniel Schwierzeck { \ 26423ff8633SDaniel Schwierzeck volatile type *__mem; \ 26523ff8633SDaniel Schwierzeck type __val; \ 26623ff8633SDaniel Schwierzeck \ 26723ff8633SDaniel Schwierzeck war_octeon_io_reorder_wmb(); \ 26823ff8633SDaniel Schwierzeck \ 26923ff8633SDaniel Schwierzeck __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 27023ff8633SDaniel Schwierzeck \ 27123ff8633SDaniel Schwierzeck __val = pfx##ioswab##bwlq(__mem, val); \ 27223ff8633SDaniel Schwierzeck \ 27323ff8633SDaniel Schwierzeck if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 27423ff8633SDaniel Schwierzeck *__mem = __val; \ 27523ff8633SDaniel Schwierzeck else if (cpu_has_64bits) { \ 27623ff8633SDaniel Schwierzeck type __tmp; \ 27723ff8633SDaniel Schwierzeck \ 27823ff8633SDaniel Schwierzeck __asm__ __volatile__( \ 27923ff8633SDaniel Schwierzeck ".set arch=r4000" "\t\t# __writeq""\n\t" \ 28023ff8633SDaniel Schwierzeck "dsll32 %L0, %L0, 0" "\n\t" \ 28123ff8633SDaniel Schwierzeck "dsrl32 %L0, %L0, 0" "\n\t" \ 28223ff8633SDaniel Schwierzeck "dsll32 %M0, %M0, 0" "\n\t" \ 28323ff8633SDaniel Schwierzeck "or %L0, %L0, %M0" "\n\t" \ 28423ff8633SDaniel Schwierzeck "sd %L0, %2" "\n\t" \ 28523ff8633SDaniel Schwierzeck ".set mips0" "\n" \ 28623ff8633SDaniel Schwierzeck : "=r" (__tmp) \ 28723ff8633SDaniel Schwierzeck : "0" (__val), "m" (*__mem)); \ 28823ff8633SDaniel Schwierzeck } else \ 28923ff8633SDaniel Schwierzeck BUG(); \ 29023ff8633SDaniel Schwierzeck } \ 29123ff8633SDaniel Schwierzeck \ 29223ff8633SDaniel Schwierzeck static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 29323ff8633SDaniel Schwierzeck { \ 29423ff8633SDaniel Schwierzeck volatile type *__mem; \ 29523ff8633SDaniel Schwierzeck type __val; \ 29623ff8633SDaniel Schwierzeck \ 29723ff8633SDaniel Schwierzeck __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 29823ff8633SDaniel Schwierzeck \ 29923ff8633SDaniel Schwierzeck if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 30023ff8633SDaniel Schwierzeck __val = *__mem; \ 30123ff8633SDaniel Schwierzeck else if (cpu_has_64bits) { \ 30223ff8633SDaniel Schwierzeck __asm__ __volatile__( \ 30323ff8633SDaniel Schwierzeck ".set arch=r4000" "\t\t# __readq" "\n\t" \ 30423ff8633SDaniel Schwierzeck "ld %L0, %1" "\n\t" \ 30523ff8633SDaniel Schwierzeck "dsra32 %M0, %L0, 0" "\n\t" \ 30623ff8633SDaniel Schwierzeck "sll %L0, %L0, 0" "\n\t" \ 30723ff8633SDaniel Schwierzeck ".set mips0" "\n" \ 30823ff8633SDaniel Schwierzeck : "=r" (__val) \ 30923ff8633SDaniel Schwierzeck : "m" (*__mem)); \ 31023ff8633SDaniel Schwierzeck } else { \ 31123ff8633SDaniel Schwierzeck __val = 0; \ 31223ff8633SDaniel Schwierzeck BUG(); \ 31323ff8633SDaniel Schwierzeck } \ 31423ff8633SDaniel Schwierzeck \ 31523ff8633SDaniel Schwierzeck return pfx##ioswab##bwlq(__mem, __val); \ 31623ff8633SDaniel Schwierzeck } 31723ff8633SDaniel Schwierzeck 31823ff8633SDaniel Schwierzeck #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 31923ff8633SDaniel Schwierzeck \ 32023ff8633SDaniel Schwierzeck static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 32123ff8633SDaniel Schwierzeck { \ 32223ff8633SDaniel Schwierzeck volatile type *__addr; \ 32323ff8633SDaniel Schwierzeck type __val; \ 32423ff8633SDaniel Schwierzeck \ 32523ff8633SDaniel Schwierzeck war_octeon_io_reorder_wmb(); \ 32623ff8633SDaniel Schwierzeck \ 32723ff8633SDaniel Schwierzeck __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 32823ff8633SDaniel Schwierzeck \ 32923ff8633SDaniel Schwierzeck __val = pfx##ioswab##bwlq(__addr, val); \ 33023ff8633SDaniel Schwierzeck \ 33123ff8633SDaniel Schwierzeck /* Really, we want this to be atomic */ \ 33223ff8633SDaniel Schwierzeck BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 33323ff8633SDaniel Schwierzeck \ 33423ff8633SDaniel Schwierzeck *__addr = __val; \ 33523ff8633SDaniel Schwierzeck slow; \ 33623ff8633SDaniel Schwierzeck } \ 33723ff8633SDaniel Schwierzeck \ 33823ff8633SDaniel Schwierzeck static inline type pfx##in##bwlq##p(unsigned long port) \ 33923ff8633SDaniel Schwierzeck { \ 34023ff8633SDaniel Schwierzeck volatile type *__addr; \ 34123ff8633SDaniel Schwierzeck type __val; \ 34223ff8633SDaniel Schwierzeck \ 34323ff8633SDaniel Schwierzeck __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 34423ff8633SDaniel Schwierzeck \ 34523ff8633SDaniel Schwierzeck BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 34623ff8633SDaniel Schwierzeck \ 34723ff8633SDaniel Schwierzeck __val = *__addr; \ 34823ff8633SDaniel Schwierzeck slow; \ 34923ff8633SDaniel Schwierzeck \ 35023ff8633SDaniel Schwierzeck return pfx##ioswab##bwlq(__addr, __val); \ 35123ff8633SDaniel Schwierzeck } 35223ff8633SDaniel Schwierzeck 35323ff8633SDaniel Schwierzeck #define __BUILD_MEMORY_PFX(bus, bwlq, type) \ 35423ff8633SDaniel Schwierzeck \ 35523ff8633SDaniel Schwierzeck __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) 35623ff8633SDaniel Schwierzeck 35723ff8633SDaniel Schwierzeck #define BUILDIO_MEM(bwlq, type) \ 35823ff8633SDaniel Schwierzeck \ 35923ff8633SDaniel Schwierzeck __BUILD_MEMORY_PFX(__raw_, bwlq, type) \ 36023ff8633SDaniel Schwierzeck __BUILD_MEMORY_PFX(, bwlq, type) \ 36123ff8633SDaniel Schwierzeck __BUILD_MEMORY_PFX(__mem_, bwlq, type) \ 36223ff8633SDaniel Schwierzeck 36323ff8633SDaniel Schwierzeck BUILDIO_MEM(b, u8) 36423ff8633SDaniel Schwierzeck BUILDIO_MEM(w, u16) 36523ff8633SDaniel Schwierzeck BUILDIO_MEM(l, u32) 36623ff8633SDaniel Schwierzeck BUILDIO_MEM(q, u64) 36723ff8633SDaniel Schwierzeck 36823ff8633SDaniel Schwierzeck #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 36923ff8633SDaniel Schwierzeck __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 37023ff8633SDaniel Schwierzeck __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 37123ff8633SDaniel Schwierzeck 37223ff8633SDaniel Schwierzeck #define BUILDIO_IOPORT(bwlq, type) \ 37323ff8633SDaniel Schwierzeck __BUILD_IOPORT_PFX(, bwlq, type) \ 37423ff8633SDaniel Schwierzeck __BUILD_IOPORT_PFX(__mem_, bwlq, type) 37523ff8633SDaniel Schwierzeck 37623ff8633SDaniel Schwierzeck BUILDIO_IOPORT(b, u8) 37723ff8633SDaniel Schwierzeck BUILDIO_IOPORT(w, u16) 37823ff8633SDaniel Schwierzeck BUILDIO_IOPORT(l, u32) 37923ff8633SDaniel Schwierzeck #ifdef CONFIG_64BIT 38023ff8633SDaniel Schwierzeck BUILDIO_IOPORT(q, u64) 38123ff8633SDaniel Schwierzeck #endif 38223ff8633SDaniel Schwierzeck 38323ff8633SDaniel Schwierzeck #define __BUILDIO(bwlq, type) \ 38423ff8633SDaniel Schwierzeck \ 38523ff8633SDaniel Schwierzeck __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) 38623ff8633SDaniel Schwierzeck 38723ff8633SDaniel Schwierzeck __BUILDIO(q, u64) 38823ff8633SDaniel Schwierzeck 38923ff8633SDaniel Schwierzeck #define readb_relaxed readb 39023ff8633SDaniel Schwierzeck #define readw_relaxed readw 39123ff8633SDaniel Schwierzeck #define readl_relaxed readl 39223ff8633SDaniel Schwierzeck #define readq_relaxed readq 39323ff8633SDaniel Schwierzeck 39423ff8633SDaniel Schwierzeck #define writeb_relaxed writeb 39523ff8633SDaniel Schwierzeck #define writew_relaxed writew 39623ff8633SDaniel Schwierzeck #define writel_relaxed writel 39723ff8633SDaniel Schwierzeck #define writeq_relaxed writeq 39823ff8633SDaniel Schwierzeck 39923ff8633SDaniel Schwierzeck #define readb_be(addr) \ 40023ff8633SDaniel Schwierzeck __raw_readb((__force unsigned *)(addr)) 40123ff8633SDaniel Schwierzeck #define readw_be(addr) \ 40223ff8633SDaniel Schwierzeck be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 40323ff8633SDaniel Schwierzeck #define readl_be(addr) \ 40423ff8633SDaniel Schwierzeck be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 40523ff8633SDaniel Schwierzeck #define readq_be(addr) \ 40623ff8633SDaniel Schwierzeck be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 40723ff8633SDaniel Schwierzeck 40823ff8633SDaniel Schwierzeck #define writeb_be(val, addr) \ 40923ff8633SDaniel Schwierzeck __raw_writeb((val), (__force unsigned *)(addr)) 41023ff8633SDaniel Schwierzeck #define writew_be(val, addr) \ 41123ff8633SDaniel Schwierzeck __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 41223ff8633SDaniel Schwierzeck #define writel_be(val, addr) \ 41323ff8633SDaniel Schwierzeck __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 41423ff8633SDaniel Schwierzeck #define writeq_be(val, addr) \ 41523ff8633SDaniel Schwierzeck __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 41623ff8633SDaniel Schwierzeck 41723ff8633SDaniel Schwierzeck /* 41823ff8633SDaniel Schwierzeck * Some code tests for these symbols 41923ff8633SDaniel Schwierzeck */ 42023ff8633SDaniel Schwierzeck #define readq readq 42123ff8633SDaniel Schwierzeck #define writeq writeq 42223ff8633SDaniel Schwierzeck 42323ff8633SDaniel Schwierzeck #define __BUILD_MEMORY_STRING(bwlq, type) \ 42423ff8633SDaniel Schwierzeck \ 42523ff8633SDaniel Schwierzeck static inline void writes##bwlq(volatile void __iomem *mem, \ 42623ff8633SDaniel Schwierzeck const void *addr, unsigned int count) \ 42723ff8633SDaniel Schwierzeck { \ 42823ff8633SDaniel Schwierzeck const volatile type *__addr = addr; \ 42923ff8633SDaniel Schwierzeck \ 43023ff8633SDaniel Schwierzeck while (count--) { \ 43123ff8633SDaniel Schwierzeck __mem_write##bwlq(*__addr, mem); \ 43223ff8633SDaniel Schwierzeck __addr++; \ 43323ff8633SDaniel Schwierzeck } \ 43423ff8633SDaniel Schwierzeck } \ 43523ff8633SDaniel Schwierzeck \ 43623ff8633SDaniel Schwierzeck static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 43723ff8633SDaniel Schwierzeck unsigned int count) \ 43823ff8633SDaniel Schwierzeck { \ 43923ff8633SDaniel Schwierzeck volatile type *__addr = addr; \ 44023ff8633SDaniel Schwierzeck \ 44123ff8633SDaniel Schwierzeck while (count--) { \ 44223ff8633SDaniel Schwierzeck *__addr = __mem_read##bwlq(mem); \ 44323ff8633SDaniel Schwierzeck __addr++; \ 44423ff8633SDaniel Schwierzeck } \ 44523ff8633SDaniel Schwierzeck } 44623ff8633SDaniel Schwierzeck 44723ff8633SDaniel Schwierzeck #define __BUILD_IOPORT_STRING(bwlq, type) \ 44823ff8633SDaniel Schwierzeck \ 44923ff8633SDaniel Schwierzeck static inline void outs##bwlq(unsigned long port, const void *addr, \ 45023ff8633SDaniel Schwierzeck unsigned int count) \ 45123ff8633SDaniel Schwierzeck { \ 45223ff8633SDaniel Schwierzeck const volatile type *__addr = addr; \ 45323ff8633SDaniel Schwierzeck \ 45423ff8633SDaniel Schwierzeck while (count--) { \ 45523ff8633SDaniel Schwierzeck __mem_out##bwlq(*__addr, port); \ 45623ff8633SDaniel Schwierzeck __addr++; \ 45723ff8633SDaniel Schwierzeck } \ 45823ff8633SDaniel Schwierzeck } \ 45923ff8633SDaniel Schwierzeck \ 46023ff8633SDaniel Schwierzeck static inline void ins##bwlq(unsigned long port, void *addr, \ 46123ff8633SDaniel Schwierzeck unsigned int count) \ 46223ff8633SDaniel Schwierzeck { \ 46323ff8633SDaniel Schwierzeck volatile type *__addr = addr; \ 46423ff8633SDaniel Schwierzeck \ 46523ff8633SDaniel Schwierzeck while (count--) { \ 46623ff8633SDaniel Schwierzeck *__addr = __mem_in##bwlq(port); \ 46723ff8633SDaniel Schwierzeck __addr++; \ 46823ff8633SDaniel Schwierzeck } \ 46923ff8633SDaniel Schwierzeck } 47023ff8633SDaniel Schwierzeck 47123ff8633SDaniel Schwierzeck #define BUILDSTRING(bwlq, type) \ 47223ff8633SDaniel Schwierzeck \ 47323ff8633SDaniel Schwierzeck __BUILD_MEMORY_STRING(bwlq, type) \ 47423ff8633SDaniel Schwierzeck __BUILD_IOPORT_STRING(bwlq, type) 47523ff8633SDaniel Schwierzeck 47623ff8633SDaniel Schwierzeck BUILDSTRING(b, u8) 47723ff8633SDaniel Schwierzeck BUILDSTRING(w, u16) 47823ff8633SDaniel Schwierzeck BUILDSTRING(l, u32) 47923ff8633SDaniel Schwierzeck #ifdef CONFIG_64BIT 48023ff8633SDaniel Schwierzeck BUILDSTRING(q, u64) 48123ff8633SDaniel Schwierzeck #endif 48223ff8633SDaniel Schwierzeck 48323ff8633SDaniel Schwierzeck 48423ff8633SDaniel Schwierzeck #ifdef CONFIG_CPU_CAVIUM_OCTEON 48523ff8633SDaniel Schwierzeck #define mmiowb() wmb() 48623ff8633SDaniel Schwierzeck #else 48723ff8633SDaniel Schwierzeck /* Depends on MIPS II instruction set */ 48823ff8633SDaniel Schwierzeck #define mmiowb() asm volatile ("sync" ::: "memory") 48923ff8633SDaniel Schwierzeck #endif 49023ff8633SDaniel Schwierzeck 49123ff8633SDaniel Schwierzeck static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 49223ff8633SDaniel Schwierzeck { 49323ff8633SDaniel Schwierzeck memset((void __force *)addr, val, count); 49423ff8633SDaniel Schwierzeck } 49523ff8633SDaniel Schwierzeck static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 49623ff8633SDaniel Schwierzeck { 49723ff8633SDaniel Schwierzeck memcpy(dst, (void __force *)src, count); 49823ff8633SDaniel Schwierzeck } 49923ff8633SDaniel Schwierzeck static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 50023ff8633SDaniel Schwierzeck { 50123ff8633SDaniel Schwierzeck memcpy((void __force *)dst, src, count); 50223ff8633SDaniel Schwierzeck } 50323ff8633SDaniel Schwierzeck 50423ff8633SDaniel Schwierzeck /* 50523ff8633SDaniel Schwierzeck * Read a 32-bit register that requires a 64-bit read cycle on the bus. 50623ff8633SDaniel Schwierzeck * Avoid interrupt mucking, just adjust the address for 4-byte access. 50723ff8633SDaniel Schwierzeck * Assume the addresses are 8-byte aligned. 50823ff8633SDaniel Schwierzeck */ 50923ff8633SDaniel Schwierzeck #ifdef __MIPSEB__ 51023ff8633SDaniel Schwierzeck #define __CSR_32_ADJUST 4 51123ff8633SDaniel Schwierzeck #else 51223ff8633SDaniel Schwierzeck #define __CSR_32_ADJUST 0 51323ff8633SDaniel Schwierzeck #endif 51423ff8633SDaniel Schwierzeck 51523ff8633SDaniel Schwierzeck #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 51623ff8633SDaniel Schwierzeck #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 51723ff8633SDaniel Schwierzeck 51823ff8633SDaniel Schwierzeck /* 51923ff8633SDaniel Schwierzeck * U-Boot specific 52023ff8633SDaniel Schwierzeck */ 52123ff8633SDaniel Schwierzeck #define sync() mmiowb() 52223ff8633SDaniel Schwierzeck 52323ff8633SDaniel Schwierzeck #define MAP_NOCACHE (1) 524819833afSPeter Tyser #define MAP_WRCOMBINE (0) 525819833afSPeter Tyser #define MAP_WRBACK (0) 526819833afSPeter Tyser #define MAP_WRTHROUGH (0) 527819833afSPeter Tyser 528819833afSPeter Tyser static inline void * 529819833afSPeter Tyser map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) 530819833afSPeter Tyser { 53123ff8633SDaniel Schwierzeck if (flags == MAP_NOCACHE) 53223ff8633SDaniel Schwierzeck return ioremap(paddr, len); 53323ff8633SDaniel Schwierzeck 534819833afSPeter Tyser return (void *)paddr; 535819833afSPeter Tyser } 536819833afSPeter Tyser 537819833afSPeter Tyser /* 538819833afSPeter Tyser * Take down a mapping set up by map_physmem(). 539819833afSPeter Tyser */ 540819833afSPeter Tyser static inline void unmap_physmem(void *vaddr, unsigned long flags) 541819833afSPeter Tyser { 542819833afSPeter Tyser } 543819833afSPeter Tyser 544*0e0efb40SDaniel Schwierzeck #define __BUILD_CLRBITS(bwlq, sfx, end, type) \ 545*0e0efb40SDaniel Schwierzeck \ 546*0e0efb40SDaniel Schwierzeck static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \ 547*0e0efb40SDaniel Schwierzeck { \ 548*0e0efb40SDaniel Schwierzeck type __val = __raw_read##bwlq(mem); \ 549*0e0efb40SDaniel Schwierzeck __val = end##_to_cpu(__val); \ 550*0e0efb40SDaniel Schwierzeck __val &= ~clr; \ 551*0e0efb40SDaniel Schwierzeck __val = cpu_to_##end(__val); \ 552*0e0efb40SDaniel Schwierzeck __raw_write##bwlq(__val, mem); \ 553*0e0efb40SDaniel Schwierzeck } 554*0e0efb40SDaniel Schwierzeck 555*0e0efb40SDaniel Schwierzeck #define __BUILD_SETBITS(bwlq, sfx, end, type) \ 556*0e0efb40SDaniel Schwierzeck \ 557*0e0efb40SDaniel Schwierzeck static inline void setbits_##sfx(volatile void __iomem *mem, type set) \ 558*0e0efb40SDaniel Schwierzeck { \ 559*0e0efb40SDaniel Schwierzeck type __val = __raw_read##bwlq(mem); \ 560*0e0efb40SDaniel Schwierzeck __val = end##_to_cpu(__val); \ 561*0e0efb40SDaniel Schwierzeck __val |= set; \ 562*0e0efb40SDaniel Schwierzeck __val = cpu_to_##end(__val); \ 563*0e0efb40SDaniel Schwierzeck __raw_write##bwlq(__val, mem); \ 564*0e0efb40SDaniel Schwierzeck } 565*0e0efb40SDaniel Schwierzeck 566*0e0efb40SDaniel Schwierzeck #define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \ 567*0e0efb40SDaniel Schwierzeck \ 568*0e0efb40SDaniel Schwierzeck static inline void clrsetbits_##sfx(volatile void __iomem *mem, \ 569*0e0efb40SDaniel Schwierzeck type clr, type set) \ 570*0e0efb40SDaniel Schwierzeck { \ 571*0e0efb40SDaniel Schwierzeck type __val = __raw_read##bwlq(mem); \ 572*0e0efb40SDaniel Schwierzeck __val = end##_to_cpu(__val); \ 573*0e0efb40SDaniel Schwierzeck __val &= ~clr; \ 574*0e0efb40SDaniel Schwierzeck __val |= set; \ 575*0e0efb40SDaniel Schwierzeck __val = cpu_to_##end(__val); \ 576*0e0efb40SDaniel Schwierzeck __raw_write##bwlq(__val, mem); \ 577*0e0efb40SDaniel Schwierzeck } 578*0e0efb40SDaniel Schwierzeck 579*0e0efb40SDaniel Schwierzeck #define BUILD_CLRSETBITS(bwlq, sfx, end, type) \ 580*0e0efb40SDaniel Schwierzeck \ 581*0e0efb40SDaniel Schwierzeck __BUILD_CLRBITS(bwlq, sfx, end, type) \ 582*0e0efb40SDaniel Schwierzeck __BUILD_SETBITS(bwlq, sfx, end, type) \ 583*0e0efb40SDaniel Schwierzeck __BUILD_CLRSETBITS(bwlq, sfx, end, type) 584*0e0efb40SDaniel Schwierzeck 585*0e0efb40SDaniel Schwierzeck #define __to_cpu(v) (v) 586*0e0efb40SDaniel Schwierzeck #define cpu_to__(v) (v) 587*0e0efb40SDaniel Schwierzeck 588*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(b, 8, _, u8) 589*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(w, le16, le16, u16) 590*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(w, be16, be16, u16) 591*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(w, 16, _, u16) 592*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(l, le32, le32, u32) 593*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(l, be32, be32, u32) 594*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(l, 32, _, u32) 595*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(q, le64, le64, u64) 596*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(q, be64, be64, u64) 597*0e0efb40SDaniel Schwierzeck BUILD_CLRSETBITS(q, 64, _, u64) 598*0e0efb40SDaniel Schwierzeck 599819833afSPeter Tyser #endif /* _ASM_IO_H */ 600