1 /* 2 * MIPS Coherence Manager (CM) Register Definitions 3 * 4 * Copyright (c) 2016 Imagination Technologies Ltd. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #ifndef __MIPS_ASM_CM_H__ 9 #define __MIPS_ASM_CM_H__ 10 11 /* Global Control Register (GCR) offsets */ 12 #define GCR_BASE 0x0008 13 #define GCR_BASE_UPPER 0x000c 14 #define GCR_REV 0x0030 15 #define GCR_L2_CONFIG 0x0130 16 #define GCR_L2_TAG_ADDR 0x0600 17 #define GCR_L2_TAG_ADDR_UPPER 0x0604 18 #define GCR_L2_TAG_STATE 0x0608 19 #define GCR_L2_TAG_STATE_UPPER 0x060c 20 #define GCR_L2_DATA 0x0610 21 #define GCR_L2_DATA_UPPER 0x0614 22 #define GCR_Cx_COHERENCE 0x2008 23 24 /* GCR_REV CM versions */ 25 #define GCR_REV_CM3 0x0800 26 27 /* GCR_L2_CONFIG fields */ 28 #define GCR_L2_CONFIG_ASSOC_SHIFT 0 29 #define GCR_L2_CONFIG_ASSOC_BITS 8 30 #define GCR_L2_CONFIG_LINESZ_SHIFT 8 31 #define GCR_L2_CONFIG_LINESZ_BITS 4 32 #define GCR_L2_CONFIG_SETSZ_SHIFT 12 33 #define GCR_L2_CONFIG_SETSZ_BITS 4 34 #define GCR_L2_CONFIG_BYPASS (1 << 20) 35 36 /* GCR_Cx_COHERENCE */ 37 #define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) 38 #define GCR_Cx_COHERENCE_EN (0x1 << 0) 39 40 #ifndef __ASSEMBLY__ 41 42 #include <asm/io.h> 43 44 static inline void *mips_cm_base(void) 45 { 46 return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); 47 } 48 49 static inline unsigned long mips_cm_l2_line_size(void) 50 { 51 unsigned long l2conf, line_sz; 52 53 l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); 54 55 line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; 56 line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); 57 return line_sz ? (2 << line_sz) : 0; 58 } 59 60 #endif /* !__ASSEMBLY__ */ 61 62 #endif /* __MIPS_ASM_CM_H__ */ 63