1*b2b135d9SPaul Burton /* 2*b2b135d9SPaul Burton * MIPS Coherence Manager (CM) Register Definitions 3*b2b135d9SPaul Burton * 4*b2b135d9SPaul Burton * Copyright (c) 2016 Imagination Technologies Ltd. 5*b2b135d9SPaul Burton * 6*b2b135d9SPaul Burton * SPDX-License-Identifier: GPL-2.0+ 7*b2b135d9SPaul Burton */ 8*b2b135d9SPaul Burton #ifndef __MIPS_ASM_CM_H__ 9*b2b135d9SPaul Burton #define __MIPS_ASM_CM_H__ 10*b2b135d9SPaul Burton 11*b2b135d9SPaul Burton /* Global Control Register (GCR) offsets */ 12*b2b135d9SPaul Burton #define GCR_BASE 0x0008 13*b2b135d9SPaul Burton #define GCR_BASE_UPPER 0x000c 14*b2b135d9SPaul Burton #define GCR_REV 0x0030 15*b2b135d9SPaul Burton 16*b2b135d9SPaul Burton /* GCR_REV CM versions */ 17*b2b135d9SPaul Burton #define GCR_REV_CM3 0x0800 18*b2b135d9SPaul Burton 19*b2b135d9SPaul Burton #endif /* __MIPS_ASM_CM_H__ */ 20