1b2b135d9SPaul Burton /* 2b2b135d9SPaul Burton * MIPS Coherence Manager (CM) Register Definitions 3b2b135d9SPaul Burton * 4b2b135d9SPaul Burton * Copyright (c) 2016 Imagination Technologies Ltd. 5b2b135d9SPaul Burton * 6b2b135d9SPaul Burton * SPDX-License-Identifier: GPL-2.0+ 7b2b135d9SPaul Burton */ 8b2b135d9SPaul Burton #ifndef __MIPS_ASM_CM_H__ 9b2b135d9SPaul Burton #define __MIPS_ASM_CM_H__ 10b2b135d9SPaul Burton 11b2b135d9SPaul Burton /* Global Control Register (GCR) offsets */ 12b2b135d9SPaul Burton #define GCR_BASE 0x0008 13b2b135d9SPaul Burton #define GCR_BASE_UPPER 0x000c 14b2b135d9SPaul Burton #define GCR_REV 0x0030 154baa0ab6SPaul Burton #define GCR_L2_CONFIG 0x0130 164baa0ab6SPaul Burton #define GCR_L2_TAG_ADDR 0x0600 174baa0ab6SPaul Burton #define GCR_L2_TAG_ADDR_UPPER 0x0604 184baa0ab6SPaul Burton #define GCR_L2_TAG_STATE 0x0608 194baa0ab6SPaul Burton #define GCR_L2_TAG_STATE_UPPER 0x060c 204baa0ab6SPaul Burton #define GCR_L2_DATA 0x0610 214baa0ab6SPaul Burton #define GCR_L2_DATA_UPPER 0x0614 22*7953354bSPaul Burton #define GCR_Cx_COHERENCE 0x2008 23b2b135d9SPaul Burton 24b2b135d9SPaul Burton /* GCR_REV CM versions */ 25b2b135d9SPaul Burton #define GCR_REV_CM3 0x0800 26b2b135d9SPaul Burton 274baa0ab6SPaul Burton /* GCR_L2_CONFIG fields */ 284baa0ab6SPaul Burton #define GCR_L2_CONFIG_ASSOC_SHIFT 0 294baa0ab6SPaul Burton #define GCR_L2_CONFIG_ASSOC_BITS 8 304baa0ab6SPaul Burton #define GCR_L2_CONFIG_LINESZ_SHIFT 8 314baa0ab6SPaul Burton #define GCR_L2_CONFIG_LINESZ_BITS 4 324baa0ab6SPaul Burton #define GCR_L2_CONFIG_SETSZ_SHIFT 12 334baa0ab6SPaul Burton #define GCR_L2_CONFIG_SETSZ_BITS 4 344baa0ab6SPaul Burton #define GCR_L2_CONFIG_BYPASS (1 << 20) 354baa0ab6SPaul Burton 36*7953354bSPaul Burton /* GCR_Cx_COHERENCE */ 37*7953354bSPaul Burton #define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) 38*7953354bSPaul Burton #define GCR_Cx_COHERENCE_EN (0x1 << 0) 39*7953354bSPaul Burton 404baa0ab6SPaul Burton #ifndef __ASSEMBLY__ 414baa0ab6SPaul Burton 424baa0ab6SPaul Burton #include <asm/io.h> 434baa0ab6SPaul Burton 444baa0ab6SPaul Burton static inline void *mips_cm_base(void) 454baa0ab6SPaul Burton { 464baa0ab6SPaul Burton return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); 474baa0ab6SPaul Burton } 484baa0ab6SPaul Burton 494baa0ab6SPaul Burton static inline unsigned long mips_cm_l2_line_size(void) 504baa0ab6SPaul Burton { 514baa0ab6SPaul Burton unsigned long l2conf, line_sz; 524baa0ab6SPaul Burton 534baa0ab6SPaul Burton l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); 544baa0ab6SPaul Burton 554baa0ab6SPaul Burton line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; 564baa0ab6SPaul Burton line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); 574baa0ab6SPaul Burton return line_sz ? (2 << line_sz) : 0; 584baa0ab6SPaul Burton } 594baa0ab6SPaul Burton 604baa0ab6SPaul Burton #endif /* !__ASSEMBLY__ */ 614baa0ab6SPaul Burton 62b2b135d9SPaul Burton #endif /* __MIPS_ASM_CM_H__ */ 63