1 /* 2 * Cache operations for the cache instruction. 3 * 4 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 5 * (C) Copyright 1999 Silicon Graphics, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 #ifndef __ASM_CACHEOPS_H 10 #define __ASM_CACHEOPS_H 11 12 #ifndef __ASSEMBLY__ 13 14 static inline void mips_cache(int op, const volatile void *addr) 15 { 16 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE 17 __builtin_mips_cache(op, addr); 18 #else 19 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr)); 20 #endif 21 } 22 23 #endif /* !__ASSEMBLY__ */ 24 25 /* 26 * Cache Operations available on all MIPS processors with R4000-style caches 27 */ 28 #define INDEX_INVALIDATE_I 0x00 29 #define INDEX_WRITEBACK_INV_D 0x01 30 #define INDEX_LOAD_TAG_I 0x04 31 #define INDEX_LOAD_TAG_D 0x05 32 #define INDEX_STORE_TAG_I 0x08 33 #define INDEX_STORE_TAG_D 0x09 34 #if defined(CONFIG_CPU_LOONGSON2) 35 #define HIT_INVALIDATE_I 0x00 36 #else 37 #define HIT_INVALIDATE_I 0x10 38 #endif 39 #define HIT_INVALIDATE_D 0x11 40 #define HIT_WRITEBACK_INV_D 0x15 41 42 /* 43 * R4000-specific cacheops 44 */ 45 #define CREATE_DIRTY_EXCL_D 0x0d 46 #define FILL 0x14 47 #define HIT_WRITEBACK_I 0x18 48 #define HIT_WRITEBACK_D 0x19 49 50 /* 51 * R4000SC and R4400SC-specific cacheops 52 */ 53 #define INDEX_INVALIDATE_SI 0x02 54 #define INDEX_WRITEBACK_INV_SD 0x03 55 #define INDEX_LOAD_TAG_SI 0x06 56 #define INDEX_LOAD_TAG_SD 0x07 57 #define INDEX_STORE_TAG_SI 0x0A 58 #define INDEX_STORE_TAG_SD 0x0B 59 #define CREATE_DIRTY_EXCL_SD 0x0f 60 #define HIT_INVALIDATE_SI 0x12 61 #define HIT_INVALIDATE_SD 0x13 62 #define HIT_WRITEBACK_INV_SD 0x17 63 #define HIT_WRITEBACK_SD 0x1b 64 #define HIT_SET_VIRTUAL_SI 0x1e 65 #define HIT_SET_VIRTUAL_SD 0x1f 66 67 /* 68 * R5000-specific cacheops 69 */ 70 #define R5K_PAGE_INVALIDATE_S 0x17 71 72 /* 73 * RM7000-specific cacheops 74 */ 75 #define PAGE_INVALIDATE_T 0x16 76 77 /* 78 * R10000-specific cacheops 79 * 80 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 81 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 82 */ 83 #define INDEX_WRITEBACK_INV_S 0x03 84 #define INDEX_LOAD_TAG_S 0x07 85 #define INDEX_STORE_TAG_S 0x0B 86 #define HIT_INVALIDATE_S 0x13 87 #define CACHE_BARRIER 0x14 88 #define HIT_WRITEBACK_INV_S 0x17 89 #define INDEX_LOAD_DATA_I 0x18 90 #define INDEX_LOAD_DATA_D 0x19 91 #define INDEX_LOAD_DATA_S 0x1b 92 #define INDEX_STORE_DATA_I 0x1c 93 #define INDEX_STORE_DATA_D 0x1d 94 #define INDEX_STORE_DATA_S 0x1f 95 96 #endif /* __ASM_CACHEOPS_H */ 97