1 /* 2 * Cache operations for the cache instruction. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 9 * (C) Copyright 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef __ASM_CACHEOPS_H 12 #define __ASM_CACHEOPS_H 13 14 #ifndef __ASSEMBLY__ 15 16 static inline void mips_cache(int op, const volatile void *addr) 17 { 18 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE 19 __builtin_mips_cache(op, addr); 20 #else 21 __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) 22 #endif 23 } 24 25 #endif /* !__ASSEMBLY__ */ 26 27 /* 28 * Cache Operations available on all MIPS processors with R4000-style caches 29 */ 30 #define INDEX_INVALIDATE_I 0x00 31 #define INDEX_WRITEBACK_INV_D 0x01 32 #define INDEX_LOAD_TAG_I 0x04 33 #define INDEX_LOAD_TAG_D 0x05 34 #define INDEX_STORE_TAG_I 0x08 35 #define INDEX_STORE_TAG_D 0x09 36 #if defined(CONFIG_CPU_LOONGSON2) 37 #define HIT_INVALIDATE_I 0x00 38 #else 39 #define HIT_INVALIDATE_I 0x10 40 #endif 41 #define HIT_INVALIDATE_D 0x11 42 #define HIT_WRITEBACK_INV_D 0x15 43 44 /* 45 * R4000-specific cacheops 46 */ 47 #define CREATE_DIRTY_EXCL_D 0x0d 48 #define FILL 0x14 49 #define HIT_WRITEBACK_I 0x18 50 #define HIT_WRITEBACK_D 0x19 51 52 /* 53 * R4000SC and R4400SC-specific cacheops 54 */ 55 #define INDEX_INVALIDATE_SI 0x02 56 #define INDEX_WRITEBACK_INV_SD 0x03 57 #define INDEX_LOAD_TAG_SI 0x06 58 #define INDEX_LOAD_TAG_SD 0x07 59 #define INDEX_STORE_TAG_SI 0x0A 60 #define INDEX_STORE_TAG_SD 0x0B 61 #define CREATE_DIRTY_EXCL_SD 0x0f 62 #define HIT_INVALIDATE_SI 0x12 63 #define HIT_INVALIDATE_SD 0x13 64 #define HIT_WRITEBACK_INV_SD 0x17 65 #define HIT_WRITEBACK_SD 0x1b 66 #define HIT_SET_VIRTUAL_SI 0x1e 67 #define HIT_SET_VIRTUAL_SD 0x1f 68 69 /* 70 * R5000-specific cacheops 71 */ 72 #define R5K_PAGE_INVALIDATE_S 0x17 73 74 /* 75 * RM7000-specific cacheops 76 */ 77 #define PAGE_INVALIDATE_T 0x16 78 79 /* 80 * R10000-specific cacheops 81 * 82 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 83 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 84 */ 85 #define INDEX_WRITEBACK_INV_S 0x03 86 #define INDEX_LOAD_TAG_S 0x07 87 #define INDEX_STORE_TAG_S 0x0B 88 #define HIT_INVALIDATE_S 0x13 89 #define CACHE_BARRIER 0x14 90 #define HIT_WRITEBACK_INV_S 0x17 91 #define INDEX_LOAD_DATA_I 0x18 92 #define INDEX_LOAD_DATA_D 0x19 93 #define INDEX_LOAD_DATA_S 0x1b 94 #define INDEX_STORE_DATA_I 0x1c 95 #define INDEX_STORE_DATA_D 0x1d 96 #define INDEX_STORE_DATA_S 0x1f 97 98 #endif /* __ASM_CACHEOPS_H */ 99