1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __MIPS_CACHE_H__ 8 #define __MIPS_CACHE_H__ 9 10 #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 11 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 12 13 #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) 14 15 /* 16 * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for 17 * DMA buffer alignment. Satisfy those drivers by providing it as a synonym 18 * of ARCH_DMA_MINALIGN for now. 19 */ 20 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN 21 22 #ifndef __ASSEMBLY__ 23 /** 24 * mips_cache_probe() - Probe the properties of the caches 25 * 26 * Call this to probe the properties such as line sizes of the caches 27 * present in the system, if any. This must be done before cache maintenance 28 * functions such as flush_cache may be called. 29 */ 30 void mips_cache_probe(void); 31 #endif 32 33 #endif /* __MIPS_CACHE_H__ */ 34