1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 272d4dd41SAnton Staaf /* 372d4dd41SAnton Staaf * Copyright (c) 2011 The Chromium OS Authors. 472d4dd41SAnton Staaf */ 572d4dd41SAnton Staaf 672d4dd41SAnton Staaf #ifndef __MIPS_CACHE_H__ 772d4dd41SAnton Staaf #define __MIPS_CACHE_H__ 872d4dd41SAnton Staaf 9f53830e7SDaniel Schwierzeck #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 10f53830e7SDaniel Schwierzeck #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 11f53830e7SDaniel Schwierzeck 12f53830e7SDaniel Schwierzeck #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) 1372d4dd41SAnton Staaf 1437228621SPaul Burton /* 1537228621SPaul Burton * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for 1637228621SPaul Burton * DMA buffer alignment. Satisfy those drivers by providing it as a synonym 1737228621SPaul Burton * of ARCH_DMA_MINALIGN for now. 1837228621SPaul Burton */ 1937228621SPaul Burton #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN 2037228621SPaul Burton 21e7e0469cSMarek Vasut #ifndef __ASSEMBLY__ 228cb4817dSPaul Burton /** 238cb4817dSPaul Burton * mips_cache_probe() - Probe the properties of the caches 248cb4817dSPaul Burton * 258cb4817dSPaul Burton * Call this to probe the properties such as line sizes of the caches 268cb4817dSPaul Burton * present in the system, if any. This must be done before cache maintenance 278cb4817dSPaul Burton * functions such as flush_cache may be called. 288cb4817dSPaul Burton */ 298cb4817dSPaul Burton void mips_cache_probe(void); 30e7e0469cSMarek Vasut #endif 318cb4817dSPaul Burton 3272d4dd41SAnton Staaf #endif /* __MIPS_CACHE_H__ */ 33