xref: /openbmc/u-boot/arch/mips/include/asm/cache.h (revision 72d4dd41)
1*72d4dd41SAnton Staaf /*
2*72d4dd41SAnton Staaf  * Copyright (c) 2011 The Chromium OS Authors.
3*72d4dd41SAnton Staaf  * See file CREDITS for list of people who contributed to this
4*72d4dd41SAnton Staaf  * project.
5*72d4dd41SAnton Staaf  *
6*72d4dd41SAnton Staaf  * This program is free software; you can redistribute it and/or
7*72d4dd41SAnton Staaf  * modify it under the terms of the GNU General Public License as
8*72d4dd41SAnton Staaf  * published by the Free Software Foundation; either version 2 of
9*72d4dd41SAnton Staaf  * the License, or (at your option) any later version.
10*72d4dd41SAnton Staaf  *
11*72d4dd41SAnton Staaf  * This program is distributed in the hope that it will be useful,
12*72d4dd41SAnton Staaf  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13*72d4dd41SAnton Staaf  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14*72d4dd41SAnton Staaf  * GNU General Public License for more details.
15*72d4dd41SAnton Staaf  *
16*72d4dd41SAnton Staaf  * You should have received a copy of the GNU General Public License
17*72d4dd41SAnton Staaf  * along with this program; if not, write to the Free Software
18*72d4dd41SAnton Staaf  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19*72d4dd41SAnton Staaf  * MA 02111-1307 USA
20*72d4dd41SAnton Staaf  */
21*72d4dd41SAnton Staaf 
22*72d4dd41SAnton Staaf #ifndef __MIPS_CACHE_H__
23*72d4dd41SAnton Staaf #define __MIPS_CACHE_H__
24*72d4dd41SAnton Staaf 
25*72d4dd41SAnton Staaf /*
26*72d4dd41SAnton Staaf  * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
27*72d4dd41SAnton Staaf  * that as a default for aligning DMA buffers unless the board config has
28*72d4dd41SAnton Staaf  * specified another cache line size.
29*72d4dd41SAnton Staaf  */
30*72d4dd41SAnton Staaf #ifdef CONFIG_SYS_CACHELINE_SIZE
31*72d4dd41SAnton Staaf #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
32*72d4dd41SAnton Staaf #else
33*72d4dd41SAnton Staaf #define ARCH_DMA_MINALIGN	128
34*72d4dd41SAnton Staaf #endif
35*72d4dd41SAnton Staaf 
36*72d4dd41SAnton Staaf #endif /* __MIPS_CACHE_H__ */
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