xref: /openbmc/u-boot/arch/mips/dts/qca953x.dtsi (revision a2277cc3)
1*a2277cc3SWills Wang/*
2*a2277cc3SWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3*a2277cc3SWills Wang *
4*a2277cc3SWills Wang * SPDX-License-Identifier: GPL-2.0+
5*a2277cc3SWills Wang */
6*a2277cc3SWills Wang
7*a2277cc3SWills Wang#include <dt-bindings/interrupt-controller/irq.h>
8*a2277cc3SWills Wang#include "skeleton.dtsi"
9*a2277cc3SWills Wang
10*a2277cc3SWills Wang/ {
11*a2277cc3SWills Wang	compatible = "qca,qca953x";
12*a2277cc3SWills Wang
13*a2277cc3SWills Wang	#address-cells = <1>;
14*a2277cc3SWills Wang	#size-cells = <1>;
15*a2277cc3SWills Wang
16*a2277cc3SWills Wang	cpus {
17*a2277cc3SWills Wang		#address-cells = <1>;
18*a2277cc3SWills Wang		#size-cells = <0>;
19*a2277cc3SWills Wang
20*a2277cc3SWills Wang		cpu@0 {
21*a2277cc3SWills Wang			device_type = "cpu";
22*a2277cc3SWills Wang			compatible = "mips,mips24Kc";
23*a2277cc3SWills Wang			reg = <0>;
24*a2277cc3SWills Wang		};
25*a2277cc3SWills Wang	};
26*a2277cc3SWills Wang
27*a2277cc3SWills Wang	clocks {
28*a2277cc3SWills Wang		#address-cells = <1>;
29*a2277cc3SWills Wang		#size-cells = <1>;
30*a2277cc3SWills Wang		ranges;
31*a2277cc3SWills Wang
32*a2277cc3SWills Wang		xtal: xtal {
33*a2277cc3SWills Wang			#clock-cells = <0>;
34*a2277cc3SWills Wang			compatible = "fixed-clock";
35*a2277cc3SWills Wang			clock-output-names = "xtal";
36*a2277cc3SWills Wang		};
37*a2277cc3SWills Wang	};
38*a2277cc3SWills Wang
39*a2277cc3SWills Wang	pinctrl {
40*a2277cc3SWills Wang		u-boot,dm-pre-reloc;
41*a2277cc3SWills Wang		compatible = "qca,qca953x-pinctrl";
42*a2277cc3SWills Wang		ranges;
43*a2277cc3SWills Wang		#address-cells = <1>;
44*a2277cc3SWills Wang		#size-cells = <1>;
45*a2277cc3SWills Wang		reg = <0x18040000 0x100>;
46*a2277cc3SWills Wang	};
47*a2277cc3SWills Wang
48*a2277cc3SWills Wang	ahb {
49*a2277cc3SWills Wang		compatible = "simple-bus";
50*a2277cc3SWills Wang		ranges;
51*a2277cc3SWills Wang
52*a2277cc3SWills Wang		#address-cells = <1>;
53*a2277cc3SWills Wang		#size-cells = <1>;
54*a2277cc3SWills Wang
55*a2277cc3SWills Wang		apb {
56*a2277cc3SWills Wang			compatible = "simple-bus";
57*a2277cc3SWills Wang			ranges;
58*a2277cc3SWills Wang
59*a2277cc3SWills Wang			#address-cells = <1>;
60*a2277cc3SWills Wang			#size-cells = <1>;
61*a2277cc3SWills Wang
62*a2277cc3SWills Wang			uart0: uart@18020000 {
63*a2277cc3SWills Wang				compatible = "ns16550";
64*a2277cc3SWills Wang				reg = <0x18020000 0x20>;
65*a2277cc3SWills Wang				reg-shift = <2>;
66*a2277cc3SWills Wang				clock-frequency = <25000000>;
67*a2277cc3SWills Wang				interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
68*a2277cc3SWills Wang
69*a2277cc3SWills Wang				status = "disabled";
70*a2277cc3SWills Wang			};
71*a2277cc3SWills Wang		};
72*a2277cc3SWills Wang
73*a2277cc3SWills Wang		spi0: spi@1f000000 {
74*a2277cc3SWills Wang			compatible = "qca,ar7100-spi";
75*a2277cc3SWills Wang			reg = <0x1f000000 0x10>;
76*a2277cc3SWills Wang			interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
77*a2277cc3SWills Wang
78*a2277cc3SWills Wang			status = "disabled";
79*a2277cc3SWills Wang
80*a2277cc3SWills Wang			#address-cells = <1>;
81*a2277cc3SWills Wang			#size-cells = <0>;
82*a2277cc3SWills Wang		};
83*a2277cc3SWills Wang	};
84*a2277cc3SWills Wang};
85