1*83d290c5STom Rini// SPDX-License-Identifier: GPL-2.0+ 2a2277cc3SWills Wang/* 3a2277cc3SWills Wang * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 4a2277cc3SWills Wang */ 5a2277cc3SWills Wang 6a2277cc3SWills Wang#include <dt-bindings/interrupt-controller/irq.h> 7a2277cc3SWills Wang#include "skeleton.dtsi" 8a2277cc3SWills Wang 9a2277cc3SWills Wang/ { 10a2277cc3SWills Wang compatible = "qca,qca953x"; 11a2277cc3SWills Wang 12a2277cc3SWills Wang #address-cells = <1>; 13a2277cc3SWills Wang #size-cells = <1>; 14a2277cc3SWills Wang 15a2277cc3SWills Wang cpus { 16a2277cc3SWills Wang #address-cells = <1>; 17a2277cc3SWills Wang #size-cells = <0>; 18a2277cc3SWills Wang 19a2277cc3SWills Wang cpu@0 { 20a2277cc3SWills Wang device_type = "cpu"; 21a2277cc3SWills Wang compatible = "mips,mips24Kc"; 22a2277cc3SWills Wang reg = <0>; 23a2277cc3SWills Wang }; 24a2277cc3SWills Wang }; 25a2277cc3SWills Wang 26a2277cc3SWills Wang clocks { 27a2277cc3SWills Wang #address-cells = <1>; 28a2277cc3SWills Wang #size-cells = <1>; 29a2277cc3SWills Wang ranges; 30a2277cc3SWills Wang 31a2277cc3SWills Wang xtal: xtal { 32a2277cc3SWills Wang #clock-cells = <0>; 33a2277cc3SWills Wang compatible = "fixed-clock"; 34a2277cc3SWills Wang clock-output-names = "xtal"; 35a2277cc3SWills Wang }; 36a2277cc3SWills Wang }; 37a2277cc3SWills Wang 38a2277cc3SWills Wang pinctrl { 39a2277cc3SWills Wang u-boot,dm-pre-reloc; 40a2277cc3SWills Wang compatible = "qca,qca953x-pinctrl"; 41a2277cc3SWills Wang ranges; 42a2277cc3SWills Wang #address-cells = <1>; 43a2277cc3SWills Wang #size-cells = <1>; 44a2277cc3SWills Wang reg = <0x18040000 0x100>; 45a2277cc3SWills Wang }; 46a2277cc3SWills Wang 47a2277cc3SWills Wang ahb { 48a2277cc3SWills Wang compatible = "simple-bus"; 49a2277cc3SWills Wang ranges; 50a2277cc3SWills Wang 51a2277cc3SWills Wang #address-cells = <1>; 52a2277cc3SWills Wang #size-cells = <1>; 53a2277cc3SWills Wang 54a2277cc3SWills Wang apb { 55a2277cc3SWills Wang compatible = "simple-bus"; 56a2277cc3SWills Wang ranges; 57a2277cc3SWills Wang 58a2277cc3SWills Wang #address-cells = <1>; 59a2277cc3SWills Wang #size-cells = <1>; 60a2277cc3SWills Wang 61a2277cc3SWills Wang uart0: uart@18020000 { 62a2277cc3SWills Wang compatible = "ns16550"; 63a2277cc3SWills Wang reg = <0x18020000 0x20>; 64a2277cc3SWills Wang reg-shift = <2>; 65a2277cc3SWills Wang clock-frequency = <25000000>; 66a2277cc3SWills Wang interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; 67a2277cc3SWills Wang 68a2277cc3SWills Wang status = "disabled"; 69a2277cc3SWills Wang }; 70a2277cc3SWills Wang }; 71a2277cc3SWills Wang 72a2277cc3SWills Wang spi0: spi@1f000000 { 73a2277cc3SWills Wang compatible = "qca,ar7100-spi"; 74a2277cc3SWills Wang reg = <0x1f000000 0x10>; 75a2277cc3SWills Wang interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; 76a2277cc3SWills Wang 77a2277cc3SWills Wang status = "disabled"; 78a2277cc3SWills Wang 79a2277cc3SWills Wang #address-cells = <1>; 80a2277cc3SWills Wang #size-cells = <0>; 81a2277cc3SWills Wang }; 82a2277cc3SWills Wang }; 83a2277cc3SWills Wang}; 84