1// SPDX-License-Identifier: GPL-2.0 2 3/ { 4 #address-cells = <1>; 5 #size-cells = <1>; 6 compatible = "ralink,mt7628a-soc"; 7 8 cpus { 9 #address-cells = <1>; 10 #size-cells = <0>; 11 12 cpu@0 { 13 compatible = "mti,mips24KEc"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 }; 18 19 resetc: reset-controller { 20 compatible = "ralink,rt2880-reset"; 21 #reset-cells = <1>; 22 }; 23 24 cpuintc: interrupt-controller { 25 #address-cells = <0>; 26 #interrupt-cells = <1>; 27 interrupt-controller; 28 compatible = "mti,cpu-interrupt-controller"; 29 }; 30 31 palmbus@10000000 { 32 compatible = "palmbus", "simple-bus"; 33 reg = <0x10000000 0x200000>; 34 ranges = <0x0 0x10000000 0x1FFFFF>; 35 36 #address-cells = <1>; 37 #size-cells = <1>; 38 39 sysc: system-controller@0 { 40 compatible = "ralink,mt7620a-sysc", "syscon"; 41 reg = <0x0 0x100>; 42 }; 43 44 syscon-reboot { 45 compatible = "syscon-reboot"; 46 regmap = <&sysc>; 47 offset = <0x34>; 48 mask = <0x1>; 49 }; 50 51 intc: interrupt-controller@200 { 52 compatible = "ralink,rt2880-intc"; 53 reg = <0x200 0x100>; 54 55 interrupt-controller; 56 #interrupt-cells = <1>; 57 58 resets = <&resetc 9>; 59 reset-names = "intc"; 60 61 interrupt-parent = <&cpuintc>; 62 interrupts = <2>; 63 64 ralink,intc-registers = <0x9c 0xa0 65 0x6c 0xa4 66 0x80 0x78>; 67 }; 68 69 memory-controller@300 { 70 compatible = "ralink,mt7620a-memc"; 71 reg = <0x300 0x100>; 72 }; 73 74 gpio@600 { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; 79 reg = <0x600 0x100>; 80 81 interrupt-parent = <&intc>; 82 interrupts = <6>; 83 84 gpio0: bank@0 { 85 reg = <0>; 86 compatible = "mtk,mt7621-gpio-bank"; 87 gpio-controller; 88 #gpio-cells = <2>; 89 }; 90 91 gpio1: bank@1 { 92 reg = <1>; 93 compatible = "mtk,mt7621-gpio-bank"; 94 gpio-controller; 95 #gpio-cells = <2>; 96 }; 97 98 gpio2: bank@2 { 99 reg = <2>; 100 compatible = "mtk,mt7621-gpio-bank"; 101 gpio-controller; 102 #gpio-cells = <2>; 103 }; 104 }; 105 106 spi0: spi@b00 { 107 compatible = "ralink,mt7621-spi"; 108 reg = <0xb00 0x40>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 clock-frequency = <200000000>; 113 }; 114 115 uart0: uartlite@c00 { 116 compatible = "ns16550a"; 117 reg = <0xc00 0x100>; 118 119 resets = <&resetc 12>; 120 reset-names = "uart0"; 121 122 interrupt-parent = <&intc>; 123 interrupts = <20>; 124 125 reg-shift = <2>; 126 }; 127 128 uart1: uart1@d00 { 129 compatible = "ns16550a"; 130 reg = <0xd00 0x100>; 131 132 resets = <&resetc 19>; 133 reset-names = "uart1"; 134 135 interrupt-parent = <&intc>; 136 interrupts = <21>; 137 138 reg-shift = <2>; 139 }; 140 141 uart2: uart2@e00 { 142 compatible = "ns16550a"; 143 reg = <0xe00 0x100>; 144 145 resets = <&resetc 20>; 146 reset-names = "uart2"; 147 148 interrupt-parent = <&intc>; 149 interrupts = <22>; 150 151 reg-shift = <2>; 152 }; 153 }; 154 155 eth@10110000 { 156 compatible = "mediatek,mt7622-eth"; 157 reg = <0x10100000 0x10000 158 0x10110000 0x8000>; 159 160 syscon = <&sysc>; 161 }; 162 163 usb_phy: usb-phy@10120000 { 164 compatible = "mediatek,mt7628-usbphy"; 165 reg = <0x10120000 0x1000>; 166 167 #phy-cells = <0>; 168 169 ralink,sysctl = <&sysc>; 170 resets = <&resetc 22 &resetc 25>; 171 reset-names = "host", "device"; 172 }; 173 174 ehci@101c0000 { 175 compatible = "generic-ehci"; 176 reg = <0x101c0000 0x1000>; 177 178 phys = <&usb_phy>; 179 phy-names = "usb"; 180 181 interrupt-parent = <&intc>; 182 interrupts = <18>; 183 }; 184}; 185