1*6787c1ecSGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*6787c1ecSGregory CLEMENT/* 3*6787c1ecSGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4*6787c1ecSGregory CLEMENT */ 5*6787c1ecSGregory CLEMENT 6*6787c1ecSGregory CLEMENT/dts-v1/; 7*6787c1ecSGregory CLEMENT#include "mscc,ocelot.dtsi" 8*6787c1ecSGregory CLEMENT 9*6787c1ecSGregory CLEMENT/ { 10*6787c1ecSGregory CLEMENT compatible = "mscc,ocelot"; 11*6787c1ecSGregory CLEMENT 12*6787c1ecSGregory CLEMENT aliases { 13*6787c1ecSGregory CLEMENT spi0 = &spi0; 14*6787c1ecSGregory CLEMENT serial0 = &uart0; 15*6787c1ecSGregory CLEMENT }; 16*6787c1ecSGregory CLEMENT 17*6787c1ecSGregory CLEMENT chosen { 18*6787c1ecSGregory CLEMENT stdout-path = "serial0:115200n8"; 19*6787c1ecSGregory CLEMENT }; 20*6787c1ecSGregory CLEMENT}; 21*6787c1ecSGregory CLEMENT 22*6787c1ecSGregory CLEMENT&uart0 { 23*6787c1ecSGregory CLEMENT status = "okay"; 24*6787c1ecSGregory CLEMENT}; 25*6787c1ecSGregory CLEMENT 26*6787c1ecSGregory CLEMENT&spi0 { 27*6787c1ecSGregory CLEMENT status = "okay"; 28*6787c1ecSGregory CLEMENT pinctrl-0 = <&spi_cs1_pin>; 29*6787c1ecSGregory CLEMENT pinctrl-names = "default"; 30*6787c1ecSGregory CLEMENT 31*6787c1ecSGregory CLEMENT spi-flash@0 { 32*6787c1ecSGregory CLEMENT compatible = "spi-flash"; 33*6787c1ecSGregory CLEMENT spi-max-frequency = <18000000>; /* input clock */ 34*6787c1ecSGregory CLEMENT reg = <0>; /* CS0 */ 35*6787c1ecSGregory CLEMENT }; 36*6787c1ecSGregory CLEMENT 37*6787c1ecSGregory CLEMENT spi-nand@1 { 38*6787c1ecSGregory CLEMENT compatible = "spi-nand"; 39*6787c1ecSGregory CLEMENT spi-max-frequency = <18000000>; /* input clock */ 40*6787c1ecSGregory CLEMENT reg = <1>; /* CS1 */ 41*6787c1ecSGregory CLEMENT }; 42*6787c1ecSGregory CLEMENT}; 43