1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "mscc,ocelot"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 compatible = "mips,mips24KEc"; 17 device_type = "cpu"; 18 clocks = <&cpu_clk>; 19 reg = <0>; 20 }; 21 }; 22 23 aliases { 24 serial0 = &uart0; 25 }; 26 27 cpuintc: interrupt-controller@0 { 28 #address-cells = <0>; 29 #interrupt-cells = <1>; 30 interrupt-controller; 31 compatible = "mti,cpu-interrupt-controller"; 32 }; 33 34 cpu_clk: cpu-clock { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <500000000>; 38 }; 39 40 sys_clk: sys-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <250000000>; 44 }; 45 46 ahb_clk: ahb-clk { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <250000000>; 50 }; 51 52 ahb { 53 compatible = "simple-bus"; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0 0x70000000 0x2000000>; 57 58 interrupt-parent = <&intc>; 59 60 cpu_ctrl: syscon@0 { 61 compatible = "mscc,ocelot-cpu-syscon", "syscon"; 62 reg = <0x0 0x2c>; 63 }; 64 65 intc: interrupt-controller@70 { 66 compatible = "mscc,ocelot-icpu-intr"; 67 reg = <0x70 0x70>; 68 #interrupt-cells = <1>; 69 interrupt-controller; 70 interrupt-parent = <&cpuintc>; 71 interrupts = <2>; 72 }; 73 74 uart0: serial@100000 { 75 pinctrl-0 = <&uart_pins>; 76 pinctrl-names = "default"; 77 compatible = "ns16550a"; 78 reg = <0x100000 0x20>; 79 interrupts = <6>; 80 clocks = <&ahb_clk>; 81 reg-io-width = <4>; 82 reg-shift = <2>; 83 84 status = "disabled"; 85 }; 86 87 uart2: serial@100800 { 88 pinctrl-0 = <&uart2_pins>; 89 pinctrl-names = "default"; 90 compatible = "ns16550a"; 91 reg = <0x100800 0x20>; 92 interrupts = <7>; 93 clocks = <&ahb_clk>; 94 reg-io-width = <4>; 95 reg-shift = <2>; 96 97 status = "disabled"; 98 }; 99 100 spi0: spi-master@101000 { 101 #address-cells = <1>; 102 #size-cells = <0>; 103 compatible = "snps,dw-apb-ssi"; 104 reg = <0x101000 0x40>; 105 num-chipselect = <4>; 106 bus-num = <0>; 107 reg-io-width = <4>; 108 reg-shift = <2>; 109 spi-max-frequency = <18000000>; /* input clock */ 110 clocks = <&ahb_clk>; 111 112 status = "disabled"; 113 }; 114 115 reset@1070008 { 116 compatible = "mscc,ocelot-chip-reset"; 117 reg = <0x1070008 0x4>; 118 }; 119 120 gpio: pinctrl@1070034 { 121 compatible = "mscc,ocelot-pinctrl"; 122 reg = <0x1070034 0x68>; 123 gpio-controller; 124 #gpio-cells = <2>; 125 gpio-ranges = <&gpio 0 0 22>; 126 127 sgpio_pins: sgpio-pins { 128 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; 129 function = "sg0"; 130 }; 131 132 uart_pins: uart-pins { 133 pins = "GPIO_6", "GPIO_7"; 134 function = "uart"; 135 }; 136 137 uart2_pins: uart2-pins { 138 pins = "GPIO_12", "GPIO_13"; 139 function = "uart2"; 140 }; 141 142 spi_cs1_pin: spi-cs1-pin { 143 pins = "GPIO_8"; 144 function = "si"; 145 }; 146 147 spi_cs2_pin: spi-cs2-pin { 148 pins = "GPIO_9"; 149 function = "si"; 150 }; 151 152 spi_cs3_pin: spi-cs3-pin { 153 pins = "GPIO_16"; 154 function = "si"; 155 }; 156 157 spi_cs4_pin: spi-cs4-pin { 158 pins = "GPIO_17"; 159 function = "si"; 160 }; 161 }; 162 163 sgpio: gpio@10700f8 { 164 compatible = "mscc,ocelot-sgpio"; 165 status = "disabled"; 166 clocks = <&sys_clk>; 167 pinctrl-0 = <&sgpio_pins>; 168 pinctrl-names = "default"; 169 reg = <0x10700f8 0x100>; 170 gpio-controller; 171 #gpio-cells = <2>; 172 gpio-ranges = <&sgpio 0 0 64>; 173 }; 174 }; 175}; 176