1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "mscc,luton"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "mips,mips24KEc"; 19 device_type = "cpu"; 20 reg = <0>; 21 }; 22 }; 23 24 aliases { 25 serial0 = &uart0; 26 }; 27 28 sys_clk: sys-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <250000000>; 32 }; 33 ahb_clk: ahb-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <208333333>; 37 }; 38 39 ahb { 40 compatible = "simple-bus"; 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0 0x60000000 0x10200000>; 44 45 uart0: serial@10100000 { 46 pinctrl-0 = <&uart_pins>; 47 pinctrl-names = "default"; 48 49 compatible = "ns16550a"; 50 reg = <0x10100000 0x20>; 51 clocks = <&ahb_clk>; 52 reg-io-width = <4>; 53 reg-shift = <2>; 54 55 status = "disabled"; 56 }; 57 58 gpio: pinctrl@70068 { 59 compatible = "mscc,luton-pinctrl"; 60 reg = <0x70068 0x68>; 61 gpio-controller; 62 #gpio-cells = <2>; 63 gpio-ranges = <&gpio 0 0 32>; 64 65 sgpio_pins: sgpio-pins { 66 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; 67 function = "sio"; 68 }; 69 uart_pins: uart-pins { 70 pins = "GPIO_30", "GPIO_31"; 71 function = "uart"; 72 }; 73 }; 74 75 sgpio: gpio@70130 { 76 compatible = "mscc,luton-sgpio"; 77 status = "disabled"; 78 clocks = <&sys_clk>; 79 pinctrl-0 = <&sgpio_pins>; 80 pinctrl-names = "default"; 81 reg = <0x0070130 0x100>; 82 gpio-controller; 83 #gpio-cells = <2>; 84 gpio-ranges = <&sgpio 0 0 64>; 85 }; 86 87 spi0: spi-bitbang { 88 compatible = "mscc,luton-bb-spi"; 89 status = "okay"; 90 reg = <0x10000064 0x4>; 91 num-chipselects = <1>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 }; 95 96 switch: switch@1010000 { 97 compatible = "mscc,vsc7527-switch"; 98 reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0 99 <0x1f0000 0x0100>, // VTSS_TO_DEV_1 100 <0x200000 0x0100>, // VTSS_TO_DEV_2 101 <0x210000 0x0100>, // VTSS_TO_DEV_3 102 <0x220000 0x0100>, // VTSS_TO_DEV_4 103 <0x230000 0x0100>, // VTSS_TO_DEV_5 104 <0x240000 0x0100>, // VTSS_TO_DEV_6 105 <0x250000 0x0100>, // VTSS_TO_DEV_7 106 <0x260000 0x0100>, // VTSS_TO_DEV_8 107 <0x270000 0x0100>, // VTSS_TO_DEV_9 108 <0x280000 0x0100>, // VTSS_TO_DEV_10 109 <0x290000 0x0100>, // VTSS_TO_DEV_11 110 <0x2a0000 0x0100>, // VTSS_TO_DEV_12 111 <0x2b0000 0x0100>, // VTSS_TO_DEV_13 112 <0x2c0000 0x0100>, // VTSS_TO_DEV_14 113 <0x2d0000 0x0100>, // VTSS_TO_DEV_15 114 <0x2e0000 0x0100>, // VTSS_TO_DEV_16 115 <0x2f0000 0x0100>, // VTSS_TO_DEV_17 116 <0x300000 0x0100>, // VTSS_TO_DEV_18 117 <0x310000 0x0100>, // VTSS_TO_DEV_19 118 <0x320000 0x0100>, // VTSS_TO_DEV_20 119 <0x330000 0x0100>, // VTSS_TO_DEV_21 120 <0x340000 0x0100>, // VTSS_TO_DEV_22 121 <0x350000 0x0100>, // VTSS_TO_DEV_23 122 <0x010000 0x1000>, // VTSS_TO_SYS 123 <0x020000 0x1000>, // VTSS_TO_ANA 124 <0x030000 0x1000>, // VTSS_TO_REW 125 <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB 126 <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS 127 <0x0a0000 0x0100>; // VTSS_TO_HSIO 128 reg-names = "port0", "port1", "port2", "port3", 129 "port4", "port5", "port6", "port7", 130 "port8", "port9", "port10", "port11", 131 "port12", "port13", "port14", "port15", 132 "port16", "port17", "port18", "port19", 133 "port20", "port21", "port22", "port23", 134 "sys", "ana", "rew", "gcb", "qs", "hsio"; 135 status = "okay"; 136 137 ethernet-ports { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 port0: port@0 { 142 reg = <0>; 143 }; 144 port1: port@1 { 145 reg = <1>; 146 }; 147 port2: port@2 { 148 reg = <2>; 149 }; 150 port3: port@3 { 151 reg = <3>; 152 }; 153 port4: port@4 { 154 reg = <4>; 155 }; 156 port5: port@5 { 157 reg = <5>; 158 }; 159 port6: port@6 { 160 reg = <6>; 161 }; 162 port7: port@7 { 163 reg = <7>; 164 }; 165 port8: port@8 { 166 reg = <8>; 167 }; 168 port9: port@9 { 169 reg = <9>; 170 }; 171 port10: port@10 { 172 reg = <10>; 173 }; 174 port11: port@11 { 175 reg = <11>; 176 }; 177 port12: port@12 { 178 reg = <12>; 179 }; 180 port13: port@13 { 181 reg = <13>; 182 }; 183 port14: port@14 { 184 reg = <14>; 185 }; 186 port15: port@15 { 187 reg = <15>; 188 }; 189 port16: port@16 { 190 reg = <16>; 191 }; 192 port17: port@17 { 193 reg = <17>; 194 }; 195 port18: port@18 { 196 reg = <18>; 197 }; 198 port19: port@19 { 199 reg = <19>; 200 }; 201 port20: port@20 { 202 reg = <20>; 203 }; 204 port21: port@21 { 205 reg = <21>; 206 }; 207 port22: port@22 { 208 reg = <22>; 209 }; 210 port23: port@23 { 211 reg = <23>; 212 }; 213 }; 214 }; 215 216 mdio0: mdio@700a0 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "mscc,luton-miim"; 220 reg = <0x700a0 0x24>; 221 status = "disabled"; 222 223 phy0: ethernet-phy@0 { 224 reg = <0>; 225 }; 226 phy1: ethernet-phy@1 { 227 reg = <1>; 228 }; 229 phy2: ethernet-phy@2 { 230 reg = <2>; 231 }; 232 phy3: ethernet-phy@3 { 233 reg = <3>; 234 }; 235 phy4: ethernet-phy@4 { 236 reg = <4>; 237 }; 238 phy5: ethernet-phy@5 { 239 reg = <5>; 240 }; 241 phy6: ethernet-phy@6 { 242 reg = <6>; 243 }; 244 phy7: ethernet-phy@7 { 245 reg = <7>; 246 }; 247 phy8: ethernet-phy@8 { 248 reg = <8>; 249 }; 250 phy9: ethernet-phy@9 { 251 reg = <9>; 252 }; 253 phy10: ethernet-phy@10 { 254 reg = <10>; 255 }; 256 phy11: ethernet-phy@11 { 257 reg = <11>; 258 }; 259 }; 260 }; 261}; 262