1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "mscc,luton"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 compatible = "mips,mips24KEc"; 19 device_type = "cpu"; 20 reg = <0>; 21 }; 22 }; 23 24 aliases { 25 serial0 = &uart0; 26 }; 27 28 sys_clk: sys-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <250000000>; 32 }; 33 ahb_clk: ahb-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <208333333>; 37 }; 38 39 ahb { 40 compatible = "simple-bus"; 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0 0x60000000 0x10200000>; 44 45 uart0: serial@10100000 { 46 pinctrl-0 = <&uart_pins>; 47 pinctrl-names = "default"; 48 49 compatible = "ns16550a"; 50 reg = <0x10100000 0x20>; 51 clocks = <&ahb_clk>; 52 reg-io-width = <4>; 53 reg-shift = <2>; 54 55 status = "disabled"; 56 }; 57 58 gpio: pinctrl@70068 { 59 compatible = "mscc,luton-pinctrl"; 60 reg = <0x70068 0x68>; 61 gpio-controller; 62 #gpio-cells = <2>; 63 gpio-ranges = <&gpio 0 0 32>; 64 65 sgpio_pins: sgpio-pins { 66 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; 67 function = "sio"; 68 }; 69 uart_pins: uart-pins { 70 pins = "GPIO_30", "GPIO_31"; 71 function = "uart"; 72 }; 73 }; 74 75 sgpio: gpio@70130 { 76 compatible = "mscc,luton-sgpio"; 77 status = "disabled"; 78 clocks = <&sys_clk>; 79 pinctrl-0 = <&sgpio_pins>; 80 pinctrl-names = "default"; 81 reg = <0x0070130 0x100>; 82 gpio-controller; 83 #gpio-cells = <2>; 84 gpio-ranges = <&sgpio 0 0 64>; 85 }; 86 87 spi0: spi-bitbang { 88 compatible = "mscc,luton-bb-spi"; 89 status = "okay"; 90 reg = <0x10000064 0x4>; 91 num-chipselects = <1>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 }; 95 }; 96}; 97