1*21fbb558Sryan_chen /* SPDX-License-Identifier: GPL-2.0+ */
2*21fbb558Sryan_chen /*
3*21fbb558Sryan_chen  * Copyright (C) ASPEED Technology Inc.
4*21fbb558Sryan_chen  */
5*21fbb558Sryan_chen 
6*21fbb558Sryan_chen #ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_
7*21fbb558Sryan_chen #define _ABI_MACH_ASPEED_AST2600_RESET_H_
8*21fbb558Sryan_chen 
9*21fbb558Sryan_chen #define ASPEED_RESET_FSI		(59)
10*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED58	(58)
11*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED57	(57)
12*21fbb558Sryan_chen #define ASPEED_RESET_SD			(56)
13*21fbb558Sryan_chen #define ASPEED_RESET_ADC		(55)
14*21fbb558Sryan_chen #define ASPEED_RESET_JTAG_MASTER2	(54)
15*21fbb558Sryan_chen #define ASPEED_RESET_MAC4		(53)
16*21fbb558Sryan_chen #define ASPEED_RESET_MAC3		(52)
17*21fbb558Sryan_chen #define ASPEED_RESET_RESERVE51	(51)
18*21fbb558Sryan_chen #define ASPEED_RESET_RESERVE50	(50)
19*21fbb558Sryan_chen #define ASPEED_RESET_RESERVE49	(49)
20*21fbb558Sryan_chen #define ASPEED_RESET_RESERVE48	(48)
21*21fbb558Sryan_chen #define ASPEED_RESET_RESERVE47	(47)
22*21fbb558Sryan_chen #define ASPEED_RESET_RESERVE46	(46)
23*21fbb558Sryan_chen #define ASPEED_RESET_I3C5		(45)
24*21fbb558Sryan_chen #define ASPEED_RESET_I3C4		(44)
25*21fbb558Sryan_chen #define ASPEED_RESET_I3C3		(43)
26*21fbb558Sryan_chen #define ASPEED_RESET_I3C2		(42)
27*21fbb558Sryan_chen #define ASPEED_RESET_I3C1		(41)
28*21fbb558Sryan_chen #define ASPEED_RESET_I3C0		(40)
29*21fbb558Sryan_chen #define ASPEED_RESET_I3C_DMA	(39)
30*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED38	(38)
31*21fbb558Sryan_chen #define ASPEED_RESET_PWM		(37)
32*21fbb558Sryan_chen #define ASPEED_RESET_PECI		(36)
33*21fbb558Sryan_chen #define ASPEED_RESET_MII		(35)
34*21fbb558Sryan_chen #define ASPEED_RESET_I2C		(34)
35*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED33	(33)
36*21fbb558Sryan_chen #define ASPEED_RESET_LPC		(32)
37*21fbb558Sryan_chen 
38*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED31	(31)
39*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED30	(30)
40*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED29	(29)
41*21fbb558Sryan_chen #define ASPEED_RESET_DP			(28)
42*21fbb558Sryan_chen #define ASPEED_RESET_XDMA2		(27)
43*21fbb558Sryan_chen #define ASPEED_RESET_GRAPHICS	(26)
44*21fbb558Sryan_chen #define ASPEED_RESET_XDMA1		(25)
45*21fbb558Sryan_chen #define ASPEED_RESET_MCTP2		(24)
46*21fbb558Sryan_chen #define ASPEED_RESET_MCTP1		(23)
47*21fbb558Sryan_chen #define ASPEED_RESET_JTAG_MASTER	(22)
48*21fbb558Sryan_chen #define ASPEED_RESET_PCIE_DEV_O		(21)
49*21fbb558Sryan_chen #define ASPEED_RESET_PCIE_DEV_OEN	(20)
50*21fbb558Sryan_chen #define ASPEED_RESET_PCIE_RC_O		(19)
51*21fbb558Sryan_chen #define ASPEED_RESET_PCIE_RC_OEN	(18)
52*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED17	(17)
53*21fbb558Sryan_chen #define ASEPPD_RESET_EMMC		(16)
54*21fbb558Sryan_chen #define ASPEED_RESET_UHCI		(15)
55*21fbb558Sryan_chen #define ASPEED_RESET_EHCI_P1	(14)
56*21fbb558Sryan_chen #define ASPEED_RESET_CRT		(13)
57*21fbb558Sryan_chen #define ASPEED_RESET_MAC2		(12)
58*21fbb558Sryan_chen #define ASPEED_RESET_MAC1		(11)
59*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED10	(10)
60*21fbb558Sryan_chen #define ASPEED_RESET_RVAS		(9)
61*21fbb558Sryan_chen #define ASPEED_RESET_PCI_VGA	(8)
62*21fbb558Sryan_chen #define ASPEED_RESET_2D			(7)
63*21fbb558Sryan_chen #define ASPEED_RESET_VIDEO		(6)
64*21fbb558Sryan_chen #define ASPEED_RESET_PCI_DP		(5)
65*21fbb558Sryan_chen #define ASPEED_RESET_HACE		(4)
66*21fbb558Sryan_chen #define ASPEED_RESET_EHCI_P2	(3)
67*21fbb558Sryan_chen #define ASPEED_RESET_RESERVED2	(2)
68*21fbb558Sryan_chen #define ASPEED_RESET_AHB		(1)
69*21fbb558Sryan_chen #define ASPEED_RESET_SDRAM		(0)
70*21fbb558Sryan_chen 
71*21fbb558Sryan_chen #endif  /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
72