1*8eef803aSShawn Guo /* 2*8eef803aSShawn Guo * This header provides constants for hisilicon pinctrl bindings. 3*8eef803aSShawn Guo * 4*8eef803aSShawn Guo * Copyright (c) 2015 Hisilicon Limited. 5*8eef803aSShawn Guo * Copyright (c) 2015 Linaro Limited. 6*8eef803aSShawn Guo * 7*8eef803aSShawn Guo * This program is free software; you can redistribute it and/or modify 8*8eef803aSShawn Guo * it under the terms of the GNU General Public License version 2 as 9*8eef803aSShawn Guo * published by the Free Software Foundation. 10*8eef803aSShawn Guo * 11*8eef803aSShawn Guo * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12*8eef803aSShawn Guo * kind, whether express or implied; without even the implied warranty 13*8eef803aSShawn Guo * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*8eef803aSShawn Guo * GNU General Public License for more details. 15*8eef803aSShawn Guo */ 16*8eef803aSShawn Guo 17*8eef803aSShawn Guo #ifndef _DT_BINDINGS_PINCTRL_HISI_H 18*8eef803aSShawn Guo #define _DT_BINDINGS_PINCTRL_HISI_H 19*8eef803aSShawn Guo 20*8eef803aSShawn Guo /* iomg bit definition */ 21*8eef803aSShawn Guo #define MUX_M0 0 22*8eef803aSShawn Guo #define MUX_M1 1 23*8eef803aSShawn Guo #define MUX_M2 2 24*8eef803aSShawn Guo #define MUX_M3 3 25*8eef803aSShawn Guo #define MUX_M4 4 26*8eef803aSShawn Guo #define MUX_M5 5 27*8eef803aSShawn Guo #define MUX_M6 6 28*8eef803aSShawn Guo #define MUX_M7 7 29*8eef803aSShawn Guo 30*8eef803aSShawn Guo /* iocg bit definition */ 31*8eef803aSShawn Guo #define PULL_MASK (3) 32*8eef803aSShawn Guo #define PULL_DIS (0) 33*8eef803aSShawn Guo #define PULL_UP (1 << 0) 34*8eef803aSShawn Guo #define PULL_DOWN (1 << 1) 35*8eef803aSShawn Guo 36*8eef803aSShawn Guo /* drive strength definition */ 37*8eef803aSShawn Guo #define DRIVE_MASK (7 << 4) 38*8eef803aSShawn Guo #define DRIVE1_02MA (0 << 4) 39*8eef803aSShawn Guo #define DRIVE1_04MA (1 << 4) 40*8eef803aSShawn Guo #define DRIVE1_08MA (2 << 4) 41*8eef803aSShawn Guo #define DRIVE1_10MA (3 << 4) 42*8eef803aSShawn Guo #define DRIVE2_02MA (0 << 4) 43*8eef803aSShawn Guo #define DRIVE2_04MA (1 << 4) 44*8eef803aSShawn Guo #define DRIVE2_08MA (2 << 4) 45*8eef803aSShawn Guo #define DRIVE2_10MA (3 << 4) 46*8eef803aSShawn Guo #define DRIVE3_04MA (0 << 4) 47*8eef803aSShawn Guo #define DRIVE3_08MA (1 << 4) 48*8eef803aSShawn Guo #define DRIVE3_12MA (2 << 4) 49*8eef803aSShawn Guo #define DRIVE3_16MA (3 << 4) 50*8eef803aSShawn Guo #define DRIVE3_20MA (4 << 4) 51*8eef803aSShawn Guo #define DRIVE3_24MA (5 << 4) 52*8eef803aSShawn Guo #define DRIVE3_32MA (6 << 4) 53*8eef803aSShawn Guo #define DRIVE3_40MA (7 << 4) 54*8eef803aSShawn Guo #define DRIVE4_02MA (0 << 4) 55*8eef803aSShawn Guo #define DRIVE4_04MA (2 << 4) 56*8eef803aSShawn Guo #define DRIVE4_08MA (4 << 4) 57*8eef803aSShawn Guo #define DRIVE4_10MA (6 << 4) 58*8eef803aSShawn Guo 59*8eef803aSShawn Guo /* drive strength definition for hi3660 */ 60*8eef803aSShawn Guo #define DRIVE6_MASK (15 << 4) 61*8eef803aSShawn Guo #define DRIVE6_04MA (0 << 4) 62*8eef803aSShawn Guo #define DRIVE6_12MA (4 << 4) 63*8eef803aSShawn Guo #define DRIVE6_19MA (8 << 4) 64*8eef803aSShawn Guo #define DRIVE6_27MA (10 << 4) 65*8eef803aSShawn Guo #define DRIVE6_32MA (15 << 4) 66*8eef803aSShawn Guo #define DRIVE7_02MA (0 << 4) 67*8eef803aSShawn Guo #define DRIVE7_04MA (1 << 4) 68*8eef803aSShawn Guo #define DRIVE7_06MA (2 << 4) 69*8eef803aSShawn Guo #define DRIVE7_08MA (3 << 4) 70*8eef803aSShawn Guo #define DRIVE7_10MA (4 << 4) 71*8eef803aSShawn Guo #define DRIVE7_12MA (5 << 4) 72*8eef803aSShawn Guo #define DRIVE7_14MA (6 << 4) 73*8eef803aSShawn Guo #define DRIVE7_16MA (7 << 4) 74*8eef803aSShawn Guo #endif 75