1*1154541aSMarek Vasut /* 2*1154541aSMarek Vasut * Copyright (C) 2017 Glider bvba 3*1154541aSMarek Vasut * 4*1154541aSMarek Vasut * This program is free software; you can redistribute it and/or modify 5*1154541aSMarek Vasut * it under the terms of the GNU General Public License as published by 6*1154541aSMarek Vasut * the Free Software Foundation; either version 2 of the License, or 7*1154541aSMarek Vasut * (at your option) any later version. 8*1154541aSMarek Vasut */ 9*1154541aSMarek Vasut #ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ 10*1154541aSMarek Vasut #define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ 11*1154541aSMarek Vasut 12*1154541aSMarek Vasut #include <dt-bindings/clock/renesas-cpg-mssr.h> 13*1154541aSMarek Vasut 14*1154541aSMarek Vasut /* r8a77995 CPG Core Clocks */ 15*1154541aSMarek Vasut #define R8A77995_CLK_Z2 0 16*1154541aSMarek Vasut #define R8A77995_CLK_ZG 1 17*1154541aSMarek Vasut #define R8A77995_CLK_ZTR 2 18*1154541aSMarek Vasut #define R8A77995_CLK_ZT 3 19*1154541aSMarek Vasut #define R8A77995_CLK_ZX 4 20*1154541aSMarek Vasut #define R8A77995_CLK_S0D1 5 21*1154541aSMarek Vasut #define R8A77995_CLK_S1D1 6 22*1154541aSMarek Vasut #define R8A77995_CLK_S1D2 7 23*1154541aSMarek Vasut #define R8A77995_CLK_S1D4 8 24*1154541aSMarek Vasut #define R8A77995_CLK_S2D1 9 25*1154541aSMarek Vasut #define R8A77995_CLK_S2D2 10 26*1154541aSMarek Vasut #define R8A77995_CLK_S2D4 11 27*1154541aSMarek Vasut #define R8A77995_CLK_S3D1 12 28*1154541aSMarek Vasut #define R8A77995_CLK_S3D2 13 29*1154541aSMarek Vasut #define R8A77995_CLK_S3D4 14 30*1154541aSMarek Vasut #define R8A77995_CLK_S1D4C 15 31*1154541aSMarek Vasut #define R8A77995_CLK_S3D1C 16 32*1154541aSMarek Vasut #define R8A77995_CLK_S3D2C 17 33*1154541aSMarek Vasut #define R8A77995_CLK_S3D4C 18 34*1154541aSMarek Vasut #define R8A77995_CLK_LB 19 35*1154541aSMarek Vasut #define R8A77995_CLK_CL 20 36*1154541aSMarek Vasut #define R8A77995_CLK_ZB3 21 37*1154541aSMarek Vasut #define R8A77995_CLK_ZB3D2 22 38*1154541aSMarek Vasut #define R8A77995_CLK_CR 23 39*1154541aSMarek Vasut #define R8A77995_CLK_CRD2 24 40*1154541aSMarek Vasut #define R8A77995_CLK_SD0H 25 41*1154541aSMarek Vasut #define R8A77995_CLK_SD0 26 42*1154541aSMarek Vasut #define R8A77995_CLK_SSP2 27 43*1154541aSMarek Vasut #define R8A77995_CLK_SSP1 28 44*1154541aSMarek Vasut #define R8A77995_CLK_RPC 29 45*1154541aSMarek Vasut #define R8A77995_CLK_RPCD2 30 46*1154541aSMarek Vasut #define R8A77995_CLK_ZA2 31 47*1154541aSMarek Vasut #define R8A77995_CLK_ZA8 32 48*1154541aSMarek Vasut #define R8A77995_CLK_Z2D 33 49*1154541aSMarek Vasut #define R8A77995_CLK_CANFD 34 50*1154541aSMarek Vasut #define R8A77995_CLK_MSO 35 51*1154541aSMarek Vasut #define R8A77995_CLK_R 36 52*1154541aSMarek Vasut #define R8A77995_CLK_OSC 37 53*1154541aSMarek Vasut #define R8A77995_CLK_LV0 38 54*1154541aSMarek Vasut #define R8A77995_CLK_LV1 39 55*1154541aSMarek Vasut #define R8A77995_CLK_CP 40 56*1154541aSMarek Vasut 57*1154541aSMarek Vasut #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ 58