1 /* 2 * GXBB clock tree IDs 3 */ 4 5 #ifndef __GXBB_CLKC_H 6 #define __GXBB_CLKC_H 7 8 #define CLKID_HDMI_PLL 2 9 #define CLKID_FCLK_DIV2 4 10 #define CLKID_FCLK_DIV3 5 11 #define CLKID_FCLK_DIV4 6 12 #define CLKID_GP0_PLL 9 13 #define CLKID_CLK81 12 14 #define CLKID_MPLL2 15 15 #define CLKID_SPICC 21 16 #define CLKID_I2C 22 17 #define CLKID_SAR_ADC 23 18 #define CLKID_RNG0 25 19 #define CLKID_UART0 26 20 #define CLKID_SPI 34 21 #define CLKID_ETH 36 22 #define CLKID_AIU_GLUE 38 23 #define CLKID_IEC958 39 24 #define CLKID_I2S_OUT 40 25 #define CLKID_MIXER_IFACE 44 26 #define CLKID_AIU 47 27 #define CLKID_UART1 48 28 #define CLKID_USB0 50 29 #define CLKID_USB1 51 30 #define CLKID_USB 55 31 #define CLKID_HDMI_PCLK 63 32 #define CLKID_USB1_DDR_BRIDGE 64 33 #define CLKID_USB0_DDR_BRIDGE 65 34 #define CLKID_UART2 68 35 #define CLKID_SANA 69 36 #define CLKID_GCLK_VENCI_INT0 77 37 #define CLKID_AOCLK_GATE 80 38 #define CLKID_IEC958_GATE 81 39 #define CLKID_AO_I2C 93 40 #define CLKID_SD_EMMC_A 94 41 #define CLKID_SD_EMMC_B 95 42 #define CLKID_SD_EMMC_C 96 43 #define CLKID_SAR_ADC_CLK 97 44 #define CLKID_SAR_ADC_SEL 98 45 #define CLKID_MALI_0_SEL 100 46 #define CLKID_MALI_0 102 47 #define CLKID_MALI_1_SEL 103 48 #define CLKID_MALI_1 105 49 #define CLKID_MALI 106 50 #define CLKID_CTS_AMCLK 107 51 #define CLKID_CTS_MCLK_I958 110 52 #define CLKID_CTS_I958 113 53 54 #endif /* __GXBB_CLKC_H */ 55