1*88dc4099SStefan Roese// SPDX-License-Identifier: GPL-2.0
2*88dc4099SStefan Roese/*
3*88dc4099SStefan Roese * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4*88dc4099SStefan Roese */
5*88dc4099SStefan Roese
6*88dc4099SStefan Roese/dts-v1/;
7*88dc4099SStefan Roese
8*88dc4099SStefan Roese#include "mt7628a.dtsi"
9*88dc4099SStefan Roese
10*88dc4099SStefan Roese/ {
11*88dc4099SStefan Roese	compatible = "gardena,smart-gateway-mt7688", "ralink,mt7628a-soc";
12*88dc4099SStefan Roese	model = "Gardena smart-Gateway-MT7688";
13*88dc4099SStefan Roese
14*88dc4099SStefan Roese	aliases {
15*88dc4099SStefan Roese		serial0 = &uart0;
16*88dc4099SStefan Roese		spi0 = &spi0;
17*88dc4099SStefan Roese	};
18*88dc4099SStefan Roese
19*88dc4099SStefan Roese	memory@0 {
20*88dc4099SStefan Roese		device_type = "memory";
21*88dc4099SStefan Roese		reg = <0x0 0x08000000>;
22*88dc4099SStefan Roese	};
23*88dc4099SStefan Roese
24*88dc4099SStefan Roese	chosen {
25*88dc4099SStefan Roese		bootargs = "console=ttyS0,57600";
26*88dc4099SStefan Roese		stdout-path = &uart0;
27*88dc4099SStefan Roese	};
28*88dc4099SStefan Roese};
29*88dc4099SStefan Roese
30*88dc4099SStefan Roese&uart0 {
31*88dc4099SStefan Roese	status = "okay";
32*88dc4099SStefan Roese	clock-frequency = <40000000>;
33*88dc4099SStefan Roese};
34*88dc4099SStefan Roese
35*88dc4099SStefan Roese&spi0 {
36*88dc4099SStefan Roese	status = "okay";
37*88dc4099SStefan Roese	num-cs = <2>;
38*88dc4099SStefan Roese
39*88dc4099SStefan Roese	spi-flash@0 {
40*88dc4099SStefan Roese		#address-cells = <1>;
41*88dc4099SStefan Roese		#size-cells = <1>;
42*88dc4099SStefan Roese		compatible = "spi-flash", "jedec,spi-nor";
43*88dc4099SStefan Roese		spi-max-frequency = <40000000>;
44*88dc4099SStefan Roese		reg = <0>;
45*88dc4099SStefan Roese	};
46*88dc4099SStefan Roese
47*88dc4099SStefan Roese	spi-nand@1 {
48*88dc4099SStefan Roese		#address-cells = <1>;
49*88dc4099SStefan Roese		#size-cells = <1>;
50*88dc4099SStefan Roese		compatible = "spi-nand";
51*88dc4099SStefan Roese		spi-max-frequency = <40000000>;
52*88dc4099SStefan Roese		reg = <1>;
53*88dc4099SStefan Roese	};
54*88dc4099SStefan Roese};
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