xref: /openbmc/u-boot/arch/mips/dts/brcm,bcm6362.dtsi (revision fabbeb33) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
4 */
5
6#include <dt-bindings/clock/bcm6362-clock.h>
7#include <dt-bindings/dma/bcm6362-dma.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/power-domain/bcm6362-power-domain.h>
10#include <dt-bindings/reset/bcm6362-reset.h>
11#include "skeleton.dtsi"
12
13/ {
14	compatible = "brcm,bcm6362";
15
16	aliases {
17		spi0 = &lsspi;
18		spi1 = &hsspi;
19	};
20
21	cpus {
22		reg = <0x10000000 0x4>;
23		#address-cells = <1>;
24		#size-cells = <0>;
25		u-boot,dm-pre-reloc;
26
27		cpu@0 {
28			compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
29			device_type = "cpu";
30			reg = <0>;
31			u-boot,dm-pre-reloc;
32		};
33
34		cpu@1 {
35			compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
36			device_type = "cpu";
37			reg = <1>;
38			u-boot,dm-pre-reloc;
39		};
40	};
41
42	clocks {
43		compatible = "simple-bus";
44		#address-cells = <1>;
45		#size-cells = <1>;
46		u-boot,dm-pre-reloc;
47
48		hsspi_pll: hsspi-pll {
49			compatible = "fixed-clock";
50			#clock-cells = <0>;
51			clock-frequency = <133333333>;
52		};
53
54		periph_osc: periph-osc {
55			compatible = "fixed-clock";
56			#clock-cells = <0>;
57			clock-frequency = <50000000>;
58			u-boot,dm-pre-reloc;
59		};
60
61		periph_clk: periph-clk {
62			compatible = "brcm,bcm6345-clk";
63			reg = <0x10000004 0x4>;
64			#clock-cells = <1>;
65		};
66	};
67
68	ubus {
69		compatible = "simple-bus";
70		#address-cells = <1>;
71		#size-cells = <1>;
72		u-boot,dm-pre-reloc;
73
74		pll_cntl: syscon@10000008 {
75			compatible = "syscon";
76			reg = <0x10000008 0x4>;
77		};
78
79		syscon-reboot {
80			compatible = "syscon-reboot";
81			regmap = <&pll_cntl>;
82			offset = <0x0>;
83			mask = <0x1>;
84		};
85
86		periph_rst: reset-controller@10000010 {
87			compatible = "brcm,bcm6345-reset";
88			reg = <0x10000010 0x4>;
89			#reset-cells = <1>;
90		};
91
92		wdt: watchdog@1000005c {
93			compatible = "brcm,bcm6345-wdt";
94			reg = <0x1000005c 0xc>;
95			clocks = <&periph_osc>;
96		};
97
98		wdt-reboot {
99			compatible = "wdt-reboot";
100			wdt = <&wdt>;
101		};
102
103		gpio1: gpio-controller@10000080 {
104			compatible = "brcm,bcm6345-gpio";
105			reg = <0x10000080 0x4>, <0x10000088 0x4>;
106			gpio-controller;
107			#gpio-cells = <2>;
108			ngpios = <16>;
109
110			status = "disabled";
111		};
112
113		gpio0: gpio-controller@10000084 {
114			compatible = "brcm,bcm6345-gpio";
115			reg = <0x10000084 0x4>, <0x1000008c 0x4>;
116			gpio-controller;
117			#gpio-cells = <2>;
118
119			status = "disabled";
120		};
121
122		uart0: serial@10000100 {
123			compatible = "brcm,bcm6345-uart";
124			reg = <0x10000100 0x18>;
125			clocks = <&periph_osc>;
126
127			status = "disabled";
128		};
129
130		uart1: serial@10000120 {
131			compatible = "brcm,bcm6345-uart";
132			reg = <0x10000120 0x18>;
133			clocks = <&periph_osc>;
134
135			status = "disabled";
136		};
137
138		lsspi: spi@10000800 {
139			compatible = "brcm,bcm6358-spi";
140			reg = <0x10000800 0x70c>;
141			#address-cells = <1>;
142			#size-cells = <0>;
143			clocks = <&periph_clk BCM6362_CLK_SPI>;
144			resets = <&periph_rst BCM6362_RST_SPI>;
145			spi-max-frequency = <20000000>;
146			num-cs = <8>;
147
148			status = "disabled";
149		};
150
151		hsspi: spi@10001000 {
152			compatible = "brcm,bcm6328-hsspi";
153			#address-cells = <1>;
154			#size-cells = <0>;
155			reg = <0x10001000 0x600>;
156			clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
157			clock-names = "hsspi", "pll";
158			resets = <&periph_rst BCM6362_RST_SPI>;
159			spi-max-frequency = <50000000>;
160			num-cs = <8>;
161
162			status = "disabled";
163		};
164
165		leds: led-controller@10001900 {
166			compatible = "brcm,bcm6328-leds";
167			reg = <0x10001900 0x24>;
168			#address-cells = <1>;
169			#size-cells = <0>;
170
171			status = "disabled";
172		};
173
174		periph_pwr: power-controller@10001848 {
175			compatible = "brcm,bcm6328-power-domain";
176			reg = <0x10001848 0x4>;
177			#power-domain-cells = <1>;
178		};
179
180		ehci: usb-controller@10002500 {
181			compatible = "brcm,bcm6362-ehci", "generic-ehci";
182			reg = <0x10002500 0x100>;
183			phys = <&usbh>;
184			big-endian;
185
186			status = "disabled";
187		};
188
189		ohci: usb-controller@10002600 {
190			compatible = "brcm,bcm6362-ohci", "generic-ohci";
191			reg = <0x10002600 0x100>;
192			phys = <&usbh>;
193			big-endian;
194
195			status = "disabled";
196		};
197
198		usbh: usb-phy@10002700 {
199			compatible = "brcm,bcm6368-usbh";
200			reg = <0x10002700 0x38>;
201			#phy-cells = <0>;
202			clocks = <&periph_clk BCM6362_CLK_USBH>;
203			clock-names = "usbh";
204			power-domains = <&periph_pwr BCM6362_PWR_USBH>;
205			resets = <&periph_rst BCM6362_RST_USBH>;
206
207			status = "disabled";
208		};
209
210		memory-controller@10003000 {
211			compatible = "brcm,bcm6328-mc";
212			reg = <0x10003000 0x864>;
213			u-boot,dm-pre-reloc;
214		};
215
216		iudma: dma-controller@1000d800 {
217			compatible = "brcm,bcm6368-iudma";
218			reg = <0x1000d800 0x80>,
219			      <0x1000da00 0x80>,
220			      <0x1000dc00 0x80>;
221			reg-names = "dma",
222				    "dma-channels",
223				    "dma-sram";
224			#dma-cells = <1>;
225			dma-channels = <8>;
226		};
227
228		enet: ethernet@10e00000 {
229			compatible = "brcm,bcm6368-enet";
230			#address-cells = <1>;
231			#size-cells = <0>;
232			reg = <0x10e00000 0x10000>;
233			clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
234				 <&periph_clk BCM6362_CLK_SWPKT_SAR>,
235				 <&periph_clk BCM6362_CLK_ROBOSW>;
236			resets = <&periph_rst BCM6362_RST_ENETSW>,
237				 <&periph_rst BCM6362_RST_EPHY>;
238			dmas = <&iudma BCM6362_DMA_ENETSW_RX>,
239			       <&iudma BCM6362_DMA_ENETSW_TX>;
240			dma-names = "rx",
241				    "tx";
242			brcm,num-ports = <6>;
243
244			status = "disabled";
245		};
246	};
247};
248