1/* 2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/bcm6358-clock.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/reset/bcm6358-reset.h> 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "brcm,bcm6358"; 14 15 cpus { 16 reg = <0xfffe0000 0x4>; 17 #address-cells = <1>; 18 #size-cells = <0>; 19 u-boot,dm-pre-reloc; 20 21 cpu@0 { 22 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; 23 device_type = "cpu"; 24 reg = <0>; 25 u-boot,dm-pre-reloc; 26 }; 27 28 cpu@1 { 29 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc"; 30 device_type = "cpu"; 31 reg = <1>; 32 u-boot,dm-pre-reloc; 33 }; 34 }; 35 36 clocks { 37 compatible = "simple-bus"; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 u-boot,dm-pre-reloc; 41 42 periph_osc: periph-osc { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <50000000>; 46 u-boot,dm-pre-reloc; 47 }; 48 49 periph_clk: periph-clk { 50 compatible = "brcm,bcm6345-clk"; 51 reg = <0xfffe0004 0x4>; 52 #clock-cells = <1>; 53 }; 54 }; 55 56 pflash: nor@1e000000 { 57 compatible = "cfi-flash"; 58 reg = <0x1e000000 0x2000000>; 59 bank-width = <2>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 63 status = "disabled"; 64 }; 65 66 ubus { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 u-boot,dm-pre-reloc; 71 72 pll_cntl: syscon@fffe0008 { 73 compatible = "syscon"; 74 reg = <0xfffe0008 0x4>; 75 }; 76 77 syscon-reboot { 78 compatible = "syscon-reboot"; 79 regmap = <&pll_cntl>; 80 offset = <0x0>; 81 mask = <0x1>; 82 }; 83 84 periph_rst: reset-controller@fffe0034 { 85 compatible = "brcm,bcm6345-reset"; 86 reg = <0xfffe0034 0x4>; 87 #reset-cells = <1>; 88 }; 89 90 wdt: watchdog@fffe005c { 91 compatible = "brcm,bcm6345-wdt"; 92 reg = <0xfffe005c 0xc>; 93 clocks = <&periph_osc>; 94 }; 95 96 wdt-reboot { 97 compatible = "wdt-reboot"; 98 wdt = <&wdt>; 99 }; 100 101 gpio1: gpio-controller@fffe0080 { 102 compatible = "brcm,bcm6345-gpio"; 103 reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>; 104 gpio-controller; 105 #gpio-cells = <2>; 106 ngpios = <8>; 107 108 status = "disabled"; 109 }; 110 111 gpio0: gpio-controller@fffe0084 { 112 compatible = "brcm,bcm6345-gpio"; 113 reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>; 114 gpio-controller; 115 #gpio-cells = <2>; 116 117 status = "disabled"; 118 }; 119 120 leds: led-controller@fffe00d0 { 121 compatible = "brcm,bcm6358-leds"; 122 reg = <0xfffe00d0 0x8>; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 126 status = "disabled"; 127 }; 128 129 uart0: serial@fffe0100 { 130 compatible = "brcm,bcm6345-uart"; 131 reg = <0xfffe0100 0x18>; 132 clocks = <&periph_osc>; 133 134 status = "disabled"; 135 }; 136 137 uart1: serial@fffe0120 { 138 compatible = "brcm,bcm6345-uart"; 139 reg = <0xfffe0120 0x18>; 140 clocks = <&periph_osc>; 141 142 status = "disabled"; 143 }; 144 145 memory-controller@fffe1200 { 146 compatible = "brcm,bcm6358-mc"; 147 reg = <0xfffe1200 0x4c>; 148 u-boot,dm-pre-reloc; 149 }; 150 }; 151}; 152