1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 */
5
6#include <dt-bindings/clock/bcm63268-clock.h>
7#include <dt-bindings/dma/bcm63268-dma.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/power-domain/bcm63268-power-domain.h>
10#include <dt-bindings/reset/bcm63268-reset.h>
11#include "skeleton.dtsi"
12
13/ {
14	compatible = "brcm,bcm63268";
15
16	aliases {
17		spi0 = &lsspi;
18		spi1 = &hsspi;
19	};
20
21	cpus {
22		reg = <0x10000000 0x4>;
23		#address-cells = <1>;
24		#size-cells = <0>;
25		u-boot,dm-pre-reloc;
26
27		cpu@0 {
28			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
29			device_type = "cpu";
30			reg = <0>;
31			u-boot,dm-pre-reloc;
32		};
33
34		cpu@1 {
35			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
36			device_type = "cpu";
37			reg = <1>;
38			u-boot,dm-pre-reloc;
39		};
40	};
41
42	clocks {
43		compatible = "simple-bus";
44		#address-cells = <1>;
45		#size-cells = <1>;
46		u-boot,dm-pre-reloc;
47
48		hsspi_pll: hsspi-pll {
49			compatible = "fixed-clock";
50			#clock-cells = <0>;
51			clock-frequency = <400000000>;
52		};
53
54		periph_osc: periph-osc {
55			compatible = "fixed-clock";
56			#clock-cells = <0>;
57			clock-frequency = <50000000>;
58			u-boot,dm-pre-reloc;
59		};
60
61		periph_clk: periph-clk {
62			compatible = "brcm,bcm6345-clk";
63			reg = <0x10000004 0x4>;
64			#clock-cells = <1>;
65		};
66
67		timer_clk: timer-clk {
68			compatible = "brcm,bcm6345-clk";
69			reg = <0x100000ac 0x4>;
70			#clock-cells = <1>;
71		};
72	};
73
74	ubus {
75		compatible = "simple-bus";
76		#address-cells = <1>;
77		#size-cells = <1>;
78		u-boot,dm-pre-reloc;
79
80		pll_cntl: syscon@10000008 {
81			compatible = "syscon";
82			reg = <0x10000008 0x4>;
83		};
84
85		syscon-reboot {
86			compatible = "syscon-reboot";
87			regmap = <&pll_cntl>;
88			offset = <0x0>;
89			mask = <0x1>;
90		};
91
92		periph_rst: reset-controller@10000010 {
93			compatible = "brcm,bcm6345-reset";
94			reg = <0x10000010 0x4>;
95			#reset-cells = <1>;
96		};
97
98		wdt: watchdog@1000009c {
99			compatible = "brcm,bcm6345-wdt";
100			reg = <0x1000009c 0xc>;
101			clocks = <&periph_osc>;
102		};
103
104		wdt-reboot {
105			compatible = "wdt-reboot";
106			wdt = <&wdt>;
107		};
108
109		gpio1: gpio-controller@100000c0 {
110			compatible = "brcm,bcm6345-gpio";
111			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
112			gpio-controller;
113			#gpio-cells = <2>;
114			ngpios = <20>;
115
116			status = "disabled";
117		};
118
119		gpio0: gpio-controller@100000c4 {
120			compatible = "brcm,bcm6345-gpio";
121			reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
122			gpio-controller;
123			#gpio-cells = <2>;
124
125			status = "disabled";
126		};
127
128		uart0: serial@10000180 {
129			compatible = "brcm,bcm6345-uart";
130			reg = <0x10000180 0x18>;
131			clocks = <&periph_osc>;
132
133			status = "disabled";
134		};
135
136		uart1: serial@100001a0 {
137			compatible = "brcm,bcm6345-uart";
138			reg = <0x100001a0 0x18>;
139			clocks = <&periph_osc>;
140
141			status = "disabled";
142		};
143
144		periph_pwr: power-controller@1000184c {
145			compatible = "brcm,bcm6328-power-domain";
146			reg = <0x1000184c 0x4>;
147			#power-domain-cells = <1>;
148		};
149
150		lsspi: spi@10000800 {
151			compatible = "brcm,bcm6358-spi";
152			reg = <0x10000800 0x70c>;
153			#address-cells = <1>;
154			#size-cells = <0>;
155			clocks = <&periph_clk BCM63268_CLK_SPI>;
156			resets = <&periph_rst BCM63268_RST_SPI>;
157			spi-max-frequency = <20000000>;
158			num-cs = <8>;
159
160			status = "disabled";
161		};
162
163		hsspi: spi@10001000 {
164			compatible = "brcm,bcm6328-hsspi";
165			#address-cells = <1>;
166			#size-cells = <0>;
167			reg = <0x10001000 0x600>;
168			clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
169			clock-names = "hsspi", "pll";
170			resets = <&periph_rst BCM63268_RST_SPI>;
171			spi-max-frequency = <50000000>;
172			num-cs = <8>;
173
174			status = "disabled";
175		};
176
177		leds: led-controller@10001900 {
178			compatible = "brcm,bcm6328-leds";
179			reg = <0x10001900 0x24>;
180			#address-cells = <1>;
181			#size-cells = <0>;
182
183			status = "disabled";
184		};
185
186		ehci: usb-controller@10002500 {
187			compatible = "brcm,bcm63268-ehci", "generic-ehci";
188			reg = <0x10002500 0x100>;
189			phys = <&usbh>;
190			big-endian;
191
192			status = "disabled";
193		};
194
195		ohci: usb-controller@10002600 {
196			compatible = "brcm,bcm63268-ohci", "generic-ohci";
197			reg = <0x10002600 0x100>;
198			phys = <&usbh>;
199			big-endian;
200
201			status = "disabled";
202		};
203
204		usbh: usb-phy@10002700 {
205			compatible = "brcm,bcm63268-usbh";
206			reg = <0x10002700 0x38>;
207			#phy-cells = <0>;
208			clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
209			clock-names = "usbh", "usb_ref";
210			power-domains = <&periph_pwr BCM63268_PWR_USBH>;
211			resets = <&periph_rst BCM63268_RST_USBH>;
212
213			status = "disabled";
214		};
215
216		memory-controller@10003000 {
217			compatible = "brcm,bcm6328-mc";
218			reg = <0x10003000 0x894>;
219			u-boot,dm-pre-reloc;
220		};
221
222		iudma: dma-controller@1000d800 {
223			compatible = "brcm,bcm6368-iudma";
224			reg = <0x1000d800 0x80>,
225			      <0x1000da00 0x80>,
226			      <0x1000dc00 0x80>;
227			reg-names = "dma",
228				    "dma-channels",
229				    "dma-sram";
230			#dma-cells = <1>;
231			dma-channels = <8>;
232		};
233
234		enet: ethernet@10700000 {
235			compatible = "brcm,bcm6368-enet";
236			#address-cells = <1>;
237			#size-cells = <0>;
238			reg = <0x10700000 0x10000>;
239			clocks = <&periph_clk BCM63268_CLK_GMAC>,
240				 <&periph_clk BCM63268_CLK_ROBOSW>,
241				 <&periph_clk BCM63268_CLK_ROBOSW250>,
242				 <&timer_clk BCM63268_TCLK_EPHY1>,
243				 <&timer_clk BCM63268_TCLK_EPHY2>,
244				 <&timer_clk BCM63268_TCLK_EPHY3>,
245				 <&timer_clk BCM63268_TCLK_GPHY>;
246			resets = <&periph_rst BCM63268_RST_ENETSW>,
247				 <&periph_rst BCM63268_RST_EPHY>,
248				 <&periph_rst BCM63268_RST_GPHY>;
249			dmas = <&iudma BCM63268_DMA_ENETSW_RX>,
250			       <&iudma BCM63268_DMA_ENETSW_TX>;
251			dma-names = "rx",
252				    "tx";
253			brcm,rgmii-override;
254			brcm,rgmii-timing;
255
256			status = "disabled";
257		};
258	};
259};
260