1/*
2 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include <dt-bindings/clock/bcm63268-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/power-domain/bcm63268-power-domain.h>
10#include <dt-bindings/reset/bcm63268-reset.h>
11#include "skeleton.dtsi"
12
13/ {
14	compatible = "brcm,bcm63268";
15
16	cpus {
17		reg = <0x10000000 0x4>;
18		#address-cells = <1>;
19		#size-cells = <0>;
20		u-boot,dm-pre-reloc;
21
22		cpu@0 {
23			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
24			device_type = "cpu";
25			reg = <0>;
26			u-boot,dm-pre-reloc;
27		};
28
29		cpu@1 {
30			compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
31			device_type = "cpu";
32			reg = <1>;
33			u-boot,dm-pre-reloc;
34		};
35	};
36
37	clocks {
38		compatible = "simple-bus";
39		#address-cells = <1>;
40		#size-cells = <1>;
41		u-boot,dm-pre-reloc;
42
43		periph_osc: periph-osc {
44			compatible = "fixed-clock";
45			#clock-cells = <0>;
46			clock-frequency = <50000000>;
47			u-boot,dm-pre-reloc;
48		};
49
50		periph_clk: periph-clk {
51			compatible = "brcm,bcm6345-clk";
52			reg = <0x10000004 0x4>;
53			#clock-cells = <1>;
54		};
55
56		timer_clk: timer-clk {
57			compatible = "brcm,bcm6345-clk";
58			reg = <0x100000ac 0x4>;
59			#clock-cells = <1>;
60		};
61	};
62
63	ubus {
64		compatible = "simple-bus";
65		#address-cells = <1>;
66		#size-cells = <1>;
67		u-boot,dm-pre-reloc;
68
69		pll_cntl: syscon@10000008 {
70			compatible = "syscon";
71			reg = <0x10000008 0x4>;
72		};
73
74		syscon-reboot {
75			compatible = "syscon-reboot";
76			regmap = <&pll_cntl>;
77			offset = <0x0>;
78			mask = <0x1>;
79		};
80
81		periph_rst: reset-controller@10000010 {
82			compatible = "brcm,bcm6345-reset";
83			reg = <0x10000010 0x4>;
84			#reset-cells = <1>;
85		};
86
87		wdt: watchdog@1000009c {
88			compatible = "brcm,bcm6345-wdt";
89			reg = <0x1000009c 0xc>;
90			clocks = <&periph_osc>;
91		};
92
93		wdt-reboot {
94			compatible = "wdt-reboot";
95			wdt = <&wdt>;
96		};
97
98		gpio1: gpio-controller@100000c0 {
99			compatible = "brcm,bcm6345-gpio";
100			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
101			gpio-controller;
102			#gpio-cells = <2>;
103			ngpios = <20>;
104
105			status = "disabled";
106		};
107
108		gpio0: gpio-controller@100000c4 {
109			compatible = "brcm,bcm6345-gpio";
110			reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
111			gpio-controller;
112			#gpio-cells = <2>;
113
114			status = "disabled";
115		};
116
117		uart0: serial@10000180 {
118			compatible = "brcm,bcm6345-uart";
119			reg = <0x10000180 0x18>;
120			clocks = <&periph_osc>;
121
122			status = "disabled";
123		};
124
125		uart1: serial@100001a0 {
126			compatible = "brcm,bcm6345-uart";
127			reg = <0x100001a0 0x18>;
128			clocks = <&periph_osc>;
129
130			status = "disabled";
131		};
132
133		periph_pwr: power-controller@1000184c {
134			compatible = "brcm,bcm6328-power-domain";
135			reg = <0x1000184c 0x4>;
136			#power-domain-cells = <1>;
137		};
138
139		leds: led-controller@10001900 {
140			compatible = "brcm,bcm6328-leds";
141			reg = <0x10001900 0x24>;
142			#address-cells = <1>;
143			#size-cells = <0>;
144
145			status = "disabled";
146		};
147
148		memory-controller@10003000 {
149			compatible = "brcm,bcm6328-mc";
150			reg = <0x10003000 0x894>;
151			u-boot,dm-pre-reloc;
152		};
153	};
154};
155