xref: /openbmc/u-boot/arch/mips/dts/brcm,bcm6318.dtsi (revision e23b19f4) 
1/*
2 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include <dt-bindings/clock/bcm6318-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/power-domain/bcm6318-power-domain.h>
10#include <dt-bindings/reset/bcm6318-reset.h>
11#include "skeleton.dtsi"
12
13/ {
14	compatible = "brcm,bcm6318";
15
16	aliases {
17		spi0 = &spi;
18	};
19
20	cpus {
21		reg = <0x10000000 0x4>;
22		#address-cells = <1>;
23		#size-cells = <0>;
24		u-boot,dm-pre-reloc;
25
26		cpu@0 {
27			compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
28			device_type = "cpu";
29			reg = <0>;
30			u-boot,dm-pre-reloc;
31		};
32	};
33
34	clocks {
35		compatible = "simple-bus";
36		#address-cells = <1>;
37		#size-cells = <1>;
38		u-boot,dm-pre-reloc;
39
40		hsspi_pll: hsspi-pll {
41			compatible = "fixed-clock";
42			#clock-cells = <0>;
43			clock-frequency = <250000000>;
44		};
45
46		periph_osc: periph-osc {
47			compatible = "fixed-clock";
48			#clock-cells = <0>;
49			clock-frequency = <50000000>;
50			u-boot,dm-pre-reloc;
51		};
52
53		periph_clk: periph-clk {
54			compatible = "brcm,bcm6345-clk";
55			reg = <0x10000004 0x4>;
56			#clock-cells = <1>;
57		};
58	};
59
60	ubus {
61		compatible = "simple-bus";
62		#address-cells = <1>;
63		#size-cells = <1>;
64		u-boot,dm-pre-reloc;
65
66		periph_rst: reset-controller@10000010 {
67			compatible = "brcm,bcm6345-reset";
68			reg = <0x10000010 0x4>;
69			#reset-cells = <1>;
70		};
71
72		wdt: watchdog@10000068 {
73			compatible = "brcm,bcm6345-wdt";
74			reg = <0x10000068 0xc>;
75			clocks = <&periph_osc>;
76		};
77
78		wdt-reboot {
79			compatible = "wdt-reboot";
80			wdt = <&wdt>;
81		};
82
83		pll_cntl: syscon@10000074 {
84			compatible = "syscon";
85			reg = <0x10000074 0x4>;
86		};
87
88		syscon-reboot {
89			compatible = "syscon-reboot";
90			regmap = <&pll_cntl>;
91			offset = <0x0>;
92			mask = <0x1>;
93		};
94
95		gpio1: gpio-controller@10000080 {
96			compatible = "brcm,bcm6345-gpio";
97			reg = <0x10000080 0x4>, <0x10000088 0x4>;
98			gpio-controller;
99			#gpio-cells = <2>;
100			ngpios = <18>;
101
102			status = "disabled";
103		};
104
105		gpio0: gpio-controller@10000084 {
106			compatible = "brcm,bcm6345-gpio";
107			reg = <0x10000084 0x4>, <0x1000008c 0x4>;
108			gpio-controller;
109			#gpio-cells = <2>;
110
111			status = "disabled";
112		};
113
114		uart0: serial@10000100 {
115			compatible = "brcm,bcm6345-uart";
116			reg = <0x10000100 0x18>;
117			clocks = <&periph_osc>;
118
119			status = "disabled";
120		};
121
122		leds: led-controller@10000200 {
123			compatible = "brcm,bcm6328-leds";
124			reg = <0x10000200 0x28>;
125			#address-cells = <1>;
126			#size-cells = <0>;
127
128			status = "disabled";
129		};
130
131		periph_pwr: power-controller@100008e8 {
132			compatible = "brcm,bcm6328-power-domain";
133			reg = <0x100008e8 0x4>;
134			#power-domain-cells = <1>;
135		};
136
137		spi: spi@10003000 {
138			compatible = "brcm,bcm6328-hsspi";
139			#address-cells = <1>;
140			#size-cells = <0>;
141			reg = <0x10003000 0x600>;
142			clocks = <&periph_clk BCM6318_CLK_HSSPI>, <&hsspi_pll>;
143			clock-names = "hsspi", "pll";
144			resets = <&periph_rst BCM6318_RST_SPI>;
145			spi-max-frequency = <33333334>;
146			num-cs = <3>;
147
148			status = "disabled";
149		};
150
151		memory-controller@10004000 {
152			compatible = "brcm,bcm6318-mc";
153			reg = <0x10004000 0x38>;
154			u-boot,dm-pre-reloc;
155		};
156	};
157};
158